Patents Examined by Earl N. Taylor
  • Patent number: 10714647
    Abstract: A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: July 14, 2020
    Assignee: SunPower Corporation
    Inventor: David D. Smith
  • Patent number: 10714610
    Abstract: A semiconductor device of an embodiment includes a silicon carbide layer; a gate electrode; a gate insulating layer disposed between the silicon carbide layer and the gate electrode; a first region disposed in the silicon carbide layer and containing nitrogen (N); and a second region disposed between the first region and the gate insulating layer, and containing at least one element selected from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), scandium (Sc), yttrium (Y), lanthanum (La), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu), hydrogen (H), deuterium (D), and fluorine (F).
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 14, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Ryosuke Iijima, Toshihide Ito, Shunsuke Asaba, Yukio Nakabayashi, Shigeto Fukatsu
  • Patent number: 10716207
    Abstract: An apparatus comprising a printed circuit board (PCB) that includes: a multilayer lamination of layers; vias on a surface of the PCB; and bonding pads that couple a ball grid array of an integrated circuit (IC) package to layers through the vias, wherein the bonding pads includes: first bonding pads in a first area of the PCB, each first bonding pad being coupled to a via of the vias in the first area, second bonding pads arranged in a second area of the PCB, each second bonding pad being coupled to a via of the vias in the second area, and third bonding pads arranged in a third area of the PCB, each third bonding pad being coupled to two or more vias of the vias in the third area, wherein the third area is located between the first area and the second area is disclosed.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 14, 2020
    Assignee: Innovium, Inc.
    Inventor: Yongming Xiong
  • Patent number: 10714342
    Abstract: Semiconductor devices and method of forming the same are disclosed. One of the semiconductor devices includes a substrate, a gate structure, a plug and a hard mask structure. The gate structure is disposed over the substrate. The plug is disposed over and electrically connected to the gate structure. The hard mask structure is disposed over the gate structure and includes a first hard mask layer and a second hard mask layer. The first hard mask layer surrounds and is in contact with the plug. The second hard mask layer surrounds the first hard mask layer and has a bottom surface at a height between a top surface and a bottom surface of the first hard mask layer. A material of the first hard mask layer is different from a material of the second hard mask layer.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Che Chiang, Chun-Sheng Liang, Kuo-Hua Pan
  • Patent number: 10707151
    Abstract: The present disclosure provides a through silicon via structure and a method for manufacturing the same. The through silicon via structure includes a semiconductor substrate, a shaping film, a conductive line, a barrier layer, and an insulating layer. The shaping film is disposed over a back surface of the semiconductor substrate, and is configured to maintain a planar formation of the semiconductor substrate. The conductive line is disposed through the shaping film and in the semiconductor substrate. The barrier layer surrounds the conductive line, and the insulating layer surrounds the barrier layer.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: July 7, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Ting-Cih Kang
  • Patent number: 10707433
    Abstract: A display panel, a method of manufacturing the display panel, and a display device are provided, the display panel includes a substrate; an underlayer on the substrate; a first electrode on the underlayer; an electroluminescent functional layer on the first electrode; and a second electrode on the electroluminescent functional layer, a longitudinal section of the underlayer has a contour which is concave from the first electrode toward the substrate as a whole, and in the longitudinal section, a thickness of a region of the underlayer close to a center of the panel is not greater than a thickness of a region of the underlayer close to an edge of the panel.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: July 7, 2020
    Assignees: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Yuanhui Guo
  • Patent number: 10699964
    Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Cheng Ching, Carlos H. Diaz, Jean-Pierre Colinge
  • Patent number: 10692771
    Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Roman W. Olac-Vaw, Walid M. Hafez, Chia-Hong Jan, Pei-Chi Liu
  • Patent number: 10685944
    Abstract: In accordance with an embodiment, sensor structure has a first, second, and third laminated structures. The second laminated structure is positioned between the first laminated structure and the third laminated structure. The first laminated structure includes a first portion of a first sensing element and the third laminated structure includes a second portion of the first sensing element. The second laminated structure includes spacer elements that can be used to adjust the sensitivity of the sensor structure.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: June 16, 2020
    Inventor: James Jen-Ho Wang
  • Patent number: 10672662
    Abstract: A packaging structure and a method for fabricating the packaging structure are provided. The method includes providing a wafer. The wafer has a first surface and a second surface opposing to the first surface, and the wafer includes a plurality of first chip regions and a spacing region between adjacent first chip regions. The method also includes forming a first adhesive layer adhered to the second surface of the wafer, and forming an opening penetrating through the spacing region of the wafer and a plurality of first chips in the first chip regions on sides of the opening. Further, the method includes forming a molding layer in the opening. The molding layer covers a sidewall of the first chip and exposes a top surface of the first chip.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: June 2, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Jian Gang Lu, Fu Cheng Chen
  • Patent number: 10672868
    Abstract: Methods of forming self-aligned nanowire spacer structures are described. An embodiment includes forming a channel structure comprising a first nanowire and a second nanowire. Source/drain structures are formed adjacent the channel structure, wherein a liner material is disposed on at least a portion of the sidewalls of the source/drain structures. A nanowire spacer structure is formed between the first and second nanowires, wherein the nanowire spacer comprises an oxidized portion of the liner.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Glenn Glass, Anand Murthy, Jun Sung Kang, Seiyon Kim
  • Patent number: 10665721
    Abstract: The invention provides a manufacturing method of flexible TFT backplane. The method uses a mixed solution of carbon nanotubes and metal oxide to prepare active layer (61) of TFT (T), and the temperature is lower and will not cause damage to the flexible base substrate (2), and the material of flexible base substrate (2) is not restricted. The use of vacuum equipment is reduced to save production cost. The carbon nanotubes have excellent conductivity, and the mixture with metal oxide as the active layer (61) of the TFT can improve the electron mobility. The buffer layer (3) has a silicon nitride film (31) as the lowest layer contacting the flexible base substrate (2), making good adhesion between buffer layer (3) and flexible base substrate (2). The topmost layer of the buffer layer (3) is an aluminum oxide film (33), which enables the buffer layer (3) to resist to water.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 26, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Fangmei Liu
  • Patent number: 10647085
    Abstract: A display device is disclosed, which includes: a support layer including a first surface, a second surface and a first side wall, wherein the first surface and the second surface locate at two opposite sides of the support layer, and the first side wall connects the first surface and the second surface; an adhesion layer disposed on the second surface of the support layer; a base layer disposed on the adhesion layer; and at least one transistor disposed on the base layer, wherein the adhesion layer adheres to a partial portion of the first side wall of the support layer.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: May 12, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Hsia-Ching Chu, Ming-Chien Sun, Yuan-Lin Wu
  • Patent number: 10651101
    Abstract: A support plate has a front face with an electronic chip mounted on the front face. A cover for encapsulating the electronic chip includes a front wall extending in front of the electronic chip and a peripheral wall having an end edge fixed on a peripheral area of the support plate. The support plate and the encapsulating cover define a chamber in which the electronic chip is located. A local slot is arranged to extend between the peripheral wall of the encapsulating cover and the support plate. The local slot has an exterior opening and an interior opening leading into said chamber.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: May 12, 2020
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Marika Sorrieul
  • Patent number: 10651132
    Abstract: A semiconductor device includes a wiring board, a first semiconductor chip fixed to the wiring board and having a first surface film, a second semiconductor chip having a second surface film and positioned such that the first semiconductor chip is between the second semiconductor chip and the wiring board, a supporting plate between the first and second semiconductor chips, the supporting plate having a first surface and a second surface located on the side opposite to the first surface, the second surface facing the first semiconductor chip, and supporting the second semiconductor chip, a front surface layer on the first surface and formed of the same material as the second surface film, a spacer between the wiring board and the supporting plate, and a sealing resin that covers the second semiconductor chip and the supporting plate and contacts the second surface film and the front surface layer.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 12, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshitaka Ono, Masamitsu Oshikiri
  • Patent number: 10651199
    Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: May 12, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Shinya Arai
  • Patent number: 10634958
    Abstract: Provided is a manufacturing method of a black photo spacer array substrate. In a manufacturing method of a black photo spacer array substrate, a double layer color resist structure formed with a first color resist layer and a second color resist layer is used to pad a main pad part and a sub pad part of a main photo spacer and a sub photo spacer. Then, a thickness of the main photo spacer and a thickness of the sub photo spacer are decreased to reduce the usage amount of black photo spacer material of forming the main photo spacer and the sub photo spacer to reduce the production cost. A height difference of the main photo spacer and the sub photo spacer can be achieved by decreasing a thickness of the first color resist layer under the sub pad part with a half exposure process.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: April 28, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Zhuming Deng
  • Patent number: 10636822
    Abstract: In a photoelectric-conversion element having a large light receiving region for a high-speed transfer, and a solid-state image sensor including the photoelectric-conversion element, the photoelectric-conversion element includes first to eighth charge read-out regions, which are provided at positions symmetric with respect to a center position of a light receiving region and first to eighth field-control electrodes, which are arranged on both sides of charge-transport paths extending from the center position of the light receiving region to the first to eighth charge read-out regions, respectively, and change depletion potentials of the charge-transport paths and the octuple charge-transfer channels.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: April 28, 2020
    Assignee: National University Corporation Shizuoka University
    Inventors: Shoji Kawahito, Min-Woong Seo, Keita Yasutomi, Yuya Shirakawa
  • Patent number: 10629546
    Abstract: A semiconductor device including a substrate including a central region and a peripheral region surrounding the central region, a semiconductor integrated circuit in the central region, and a three-dimensional crack detection structure in the peripheral region, the three-dimensional crack detection structure surrounding the central region, the three-dimensional crack detection structure including a first pattern, a second pattern, and a third pattern, the first and second patterns extending in a first direction and spaced apart from each other, the third pattern being parallel to an upper surface of the substrate and connecting the first and second patterns to each other, the third pattern including a first portion and a second portion, the first and second portions extending in a second direction and a third direction respectively, the second direction intersecting with the first direction, the third direction intersecting with the first and second directions may be provided.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: April 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung Hyun Roh
  • Patent number: 10620492
    Abstract: The present disclosure relates to a method for manufacturing an array substrate, an array substrate and a display device. The method includes: disposing, on a substrate, a plurality of thin film transistors arranged in an array; depositing a first transparent electrode layer on the substrate and processing the first transparent electrode layer by using a first pattern process, so as to form a plurality of first electrodes connected with drains of the film transistors, and a connecting electrode connecting adjacent ones of the first electrodes; disposing a functional structure on a side of the first transparent electrode layer that is away from the substrate; and processing the connecting electrode by using a second pattern process and disconnecting the connecting electrode, so as to form a convex connection on an edge of the first electrode.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 14, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Lei Su, Xiaofei Yang, Xu Liu, Xinghua Li