Patents Examined by Earl N. Taylor
  • Leadframe and method of making the same
    Patent number: 10600726
    Abstract: A leadframe includes first and second surfaces, a plurality of leads, and a hole-defining wall unit including a plurality of first-hole defining walls each defining a first through hole and a plurality of second-hole defining walls each defining a second through hole. Each of the first and second through holes is formed between two adjacent ones of the leads. Each of the first hole-defining walls has top and bottom edges respectively forming arcuate and burr regions with the first and surfaces at junctions therebetween. Each of the second hole-defining walls has top and bottom edges respectively forming burr and arcuate regions with the first and second surfaces at junctions therebetween.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: March 24, 2020
    Assignee: CHANG WAH TECHNOLOGY CO., LTD.
    Inventor: Chia-Neng Huang
  • Electronic switching element and modularly constructed power converter
    Patent number: 10600705
    Abstract: An electronic switching element includes at least one semiconductor switch inserted into a layer sequence of a conductor structure element; and at least two busbars which are configured to contact-connect the at least one semiconductor switch, wherein the at least two busbars run substantially above one another in the layer sequence of the conductor structure element.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: March 24, 2020
    Assignee: SCHWEIZER ELECTRONIC AG
    Inventors: Thomas Gottwald, Christian Rössle, Rainer Jäackle
  • Detector unit for detector array of radiation imaging modality
    Patent number: 10598802
    Abstract: Among other things, a detector unit for a radiation detector array is provided. The detector unit includes a radiation detection sub-assembly including a scintillator and a photodetector array. A first routing layer is coupled to the photodetector array of the radiation detection sub-assembly at a first surface of the routing layer. An electronics assembly includes an analog-to-digital converter that converts an analog signal to a digital signal. A second routing layer is disposed between the A/D converter and the first routing layer. A shielding element is disposed between the A/D converter and the second routing layer. The shielding element shields the A/D converter from the radiation photons. The second routing layer couples the electronics sub-assembly to the first routing layer. A first coupling element couples the A/D converter to the second routing layer.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: March 24, 2020
    Assignee: Analogic Corporation
    Inventors: Randy Luhta, Chris Vrettos
  • Solid-state imaging element, method of manufacturing the same, and imaging device
    Patent number: 10593721
    Abstract: In pixels that are two-dimensionally arranged in a matrix fashion in the pixel array unit of a solid-state imaging element, a photoelectric conversion film having a light shielding film buried therein is formed and stacked on the light incident side of the photodiode. The present technique can be applied to a CMOS image sensor compatible with the global shutter system, for example.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: March 17, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Kenichi Nishizawa
  • Vertical transistor with one-dimensional edge contacts
    Patent number: 10586864
    Abstract: A vertical transistor and a method of creating thereof are provided. A substrate is provided. A first electrode, comprising a two-dimensional (2D) material, is defined on top of the substrate. A spacer is deposited on top of the first electrode. A second electrode, comprising a 2D material, is defined on top of the spacer. A mask layer is formed on top of the second electrode. A channel is formed on top of the mask layer. A gate dielectric layer is provided on top of the channel. A gate coupled to the second portion of the gate dielectric is provided.
    Type: Grant
    Filed: August 5, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jianshi Tang, Qing Cao
  • Trench semiconductor device layout configurations
    Patent number: 10580861
    Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: March 3, 2020
    Assignees: POLAR SEMICONDUCTOR, LLC, SANKEN ELECTRIC CO., LTD.
    Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven Kosier, Peter West
  • Infrared detector, imaging device, imaging system, and method of manufacturing infrared detector
    Patent number: 10580916
    Abstract: An infrared detector includes, a substrate, a lower contact layer formed on the substrate, a first light receiving layer that is formed on the lower contact layer and has a quantum well structure, an intermediate contact layer formed on the first light receiving layer, a second light receiving layer that is formed on the intermediate contact layer and has a quantum well structure, and an upper contact layer formed on the second light receiving layer. Each of the first light receiving layer and the second light receiving layer includes, a first semiconductor layer that is doped with a first conductivity-type impurity, and a second semiconductor layer that is formed on the first semiconductor layer, and is doped with a second conductivity-type impurity which compensates the first conductivity-type impurity.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: March 3, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Shigekazu Okumura, Ryo Suzuki
  • Gate metal patterning to avoid gate stack attack due to excessive wet etching
    Patent number: 10573521
    Abstract: A method of forming gate structures to a nanosheet device that includes forming at least two stacks of nanosheets, wherein each nanosheet includes a channel region portion having a gate dielectric layer present thereon. The method may further include forming a dual metal layer scheme on the gate dielectric layer of each nanosheet. The dual metal layer scheme including an etch stop layer of a first composition and a work function adjusting layer of a second composition, wherein the etch stop layer has a composition that provides that the work function adjusting layer is removable by a wet etch chemistry that is selective to the etch stop layer.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junli Wang, Alexander Reznicek, Shogo Mochizuki, Joshua Rubin
  • Method for manufacturing image capturing device and image capturing device
    Patent number: 10559623
    Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: February 11, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Takahiro Tomimatsu
  • Light emitting device with reflective sidewall
    Patent number: 10559617
    Abstract: Embodiments of the invention include a semiconductor light emitting device including a semiconductor structure. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region. A wavelength converting structure is disposed in a path of light emitted by the light emitting layer. A diffuse reflector is disposed along a sidewall of the semiconductor light emitting device and the wavelength converting structure. The diffuse reflector includes a pigment. A reflective layer is disposed between the diffuse reflector and the semiconductor structure. The reflective layer is a different material from the diffuse reflector.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: February 11, 2020
    Assignee: LUMILEDS LLC
    Inventors: Dawei Lu, Oleg Shchekin
  • Patterned gate dielectrics for III-V-based CMOS circuits
    Patent number: 10553584
    Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan, John Rozen
  • Integrated chip scale packages
    Patent number: 10553511
    Abstract: Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: February 4, 2020
    Assignee: CUBIC CORPORATION
    Inventor: J. Robert Reid
  • Quantum dot device and display device
    Patent number: 10535829
    Abstract: A quantum dot device including an anode and a cathode facing each other, a quantum dot layer between the anode and the cathode and electron auxiliary layer between the quantum dot layer and the cathode, wherein the electron auxiliary layer includes at least one nanoparticle represented by Chemical Formula 1 and at least one metal halide represented by Chemical Formula 2, and a display device.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: January 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan Su Kim, Tae Ho Kim, Kun Su Park, Sung Woo Kim, Eun Joo Jang
  • Semiconductor device
    Patent number: 10535812
    Abstract: A semiconductor device includes a semiconductor element, a conductive layer, terminals, and a sealing resin. The conductive layer, containing metal particles, is in contact with the reverse surface and the side surface of the semiconductor element. The terminals are spaced apart from and electrically connected to the semiconductor element. The sealing resin covers the semiconductor element. The conductive layer has an edge located outside of the semiconductor element as viewed in plan. Each terminal includes a top surface, a bottom surface, an inner side surface held in contact with the sealing resin, and the terminal is formed with a dent portion recessed from the bottom surface and the inner side surface. The conductive layer and the bottom surface of each terminal are exposed from a bottom surface of the sealing resin.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: January 14, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Yuya Hasegawa, Satohiro Kigoshi
  • Array substrate, method for manufacturing the same, display device
    Patent number: 10534233
    Abstract: The present disclosure provides an array substrate, a method for manufacturing the same, and a display device, which belongs to the field of display technology. The array substrate includes a metal electrode layer, a pad layer, a first insulating layer and a first transparent conductive layer, wherein: the pad layer includes a transparent conductive material, the metal electrode layer includes a conductive layer and protection layers formed on both surfaces of the conductive layer, and the pad layer is connected to the metal electrode layer; the first insulating layer is covered on the metal electrode layer and the pad layer, and the first transparent conductive layer is disposed on the first insulating layer; and a via hole is provided in the first insulating layer, and the first transparent conductive layer is connected to the pad layer through the via hole.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: January 14, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Maokun Tian, Zhonghao Huang, Xu Wu
  • GaN lateral vertical JFET with regrown channel and dielectric gate
    Patent number: 10535741
    Abstract: A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has a N+ implant source region. In one embodiment, a JFET is provided with a drain metal deposited over a backside of an N substrate, an n-type drift layer epitaxial grown over a topside of the N substrate, a buried P-type block layer deposited over the n-type drift layer, an implanted N+ source region on side walls of the lateral channel layer, and an source metal attached to the top of the p-layer and attached to the implanted N+ source region at the side. In one embodiment, the JFET further comprises a gate layer, and wherein the gate layer is a dielectric gate structure that enables a fully enhanced channel. In another embodiment, the gate layer is a p-type GaN gate structure that enables a partially enhanced channel.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: January 14, 2020
    Inventor: Gangfeng Ye
  • Method and structure to construct cylindrical interconnects to reduce resistance
    Patent number: 10529662
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Michael Rizzolo, Christopher J. Penny, Huai Huang, Lawrence A. Clevenger, Hosadurga Shobha
  • Silicon-containing semiconductor structures, methods of making the same and devices including the same
    Patent number: 10529872
    Abstract: A semiconductor system includes a silicon substrate and a porous silicon region disposed on the silicon substrate. The porous silicon region is configured to passivate the surface of the silicon substrate via a field effect and to reduce reflection loss on the silicon substrate via an appropriate refractive index. The porous silicon region is manufactured by a stain etching process, which retrofits existing tools for junction isolation and Phosphorus Silicon Glass (PSG) etch in solar cell manufacturing. The retrofitted tools for junction isolation and PSG etch achieves multiple purposes in a single step, including etch-back, PSG etch, antireflection coating, and passivation of the front surface of the solar cell.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: January 7, 2020
    Assignee: SPECMAT, Inc.
    Inventors: Horia M. Faur, Maria Faur
  • Enhanced self-alignment of vias for a semiconductor device
    Patent number: 10515894
    Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Michael Rizzolo, Nicole A. Saulnier
  • Stacked photodetector assemblies
    Patent number: 10515993
    Abstract: An exemplary stacked photodetector assembly includes a first wafer and a second wafer bonded to the first wafer. The first wafer includes a SPAD and has a thickness T1 configured to minimize absorption by the first wafer of photons included in light incident upon the first wafer while the SPAD is in a disarmed state. The second wafer has a thickness T2 configured to provide structural support for the first wafer. The stacked photodetector assembly includes a fast gating circuit electrically coupled to the SPAD and configured to arm and disarm the SPAD.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: December 24, 2019
    Assignee: HI LLC
    Inventors: Ryan Field, Husam Katnani, Bruno Do Valle, Rong Jin, Jacob Dahle