Abstract: A two-step hole etching method including: providing a semiconductor wafer which has a plurality of solar cell stacks and performing a first and a second processing step. In the first processing step, a first resist layer is applied to a top surface of the semiconductor wafer, at least a first opening is produced in the first resist layer and, via a first etching process, a hole which extends beyond a p/n junction of the Ge sub-cell into the semiconductor wafer is produced in the area of the first opening. In the second process step a second resist layer is applied to the top surface of the semiconductor wafer, a second opening greater than the first opening and surrounding the hole is produced in the second resist layer, and, the hole is widened in an area which extends to the Ge sub-cell serving as an etch stop layer.

Abstract: A a semiconductor storage device includes a logic circuit formed on a substrate, a first area formed on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternatively stacked in a first direction, a plurality of memory pillars MP which extend in the first area in the first direction, a second area which is formed on the logic circuit and has the plurality of first insulating layers 33 and a plurality of second insulating layers alternately stacked in the first direction, and a contact ping CP1 which extends in the second area in the first direction and is connected to the logic circuit.

Abstract: Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.

Abstract: The present disclosure relates to a method and apparatus for manufacturing a semiconductor sheet assembly. The method for manufacturing a semiconductor sheet assembly includes positioning a semiconductor sheet, and determining a first region to be grooved and a defect position in the first region; cutting and grooving the semiconductor sheet along the defect position in the first region; and splitting the semiconductor sheet that is cut and grooved.

Abstract: A method for manufacturing a solar cell capable of enhancing photoelectric conversion efficiency is provided. The present invention is a method for manufacturing a solar cell which includes steps of forming a p-n junction on a silicon semiconductor substrate and forming an aluminum oxide film on at least one main surface of the silicon semiconductor substrate, including: a step of subjecting the silicon semiconductor substrate to heat treatment in an atmosphere with 20 g or more water vapor per cubic meter and a temperature of 60° C. or more and 100° C. or less before the step of forming the aluminum oxide film. Consequently, a method for manufacturing a solar cell capable of enhancing photoelectric conversion efficiency is provided.

Abstract: A first FinFET device includes first fin structures that extend in a first direction in a top view. A second FinFET device includes second fin structures that extend in the first direction in the top view. The first FinFET device and the second FinFET device are different types of FinFET devices. A plurality of gate structures extend in a second direction in the top view. The second direction is different from the first direction. Each of the gate structures partially wraps around the first fin structures and the second fin structures. A dielectric structure is disposed between the first FinFET device and the second FinFET device. The dielectric structure cuts each of the gate structures into a first segment for the first FinFET device and a second segment for the second FinFET device. The dielectric structure is located closer to the first FinFET device than to the second FinFET device.

Abstract: Semiconductor device structures and techniques are provided for measuring contact resistance. A semiconductor device is disclosed including a first source/drain region and a contact disposed on the first source/drain region and configured to supply energy to the semiconductor device. A fin extends between the first source/drain region and a second source/drain region of the semiconductor device. A first contact material layer is disposed on the second source/drain region and a first active drain contact is disposed on the first contact material layer. A first sensor drain contact is also disposed on the first contact material layer. A second contact material layer is disposed on the second source/drain region and a second active drain contact is disposed on the second contact material layer. A third contact material layer is disposed on the second source/drain region and a second sensor drain contact is disposed on the third contact material layer.

Abstract: In a general aspect, a for producing a fan-out wafer level package (FOWLP) semiconductor device can include separating a semiconductor wafer into a plurality of semiconductor die and, after separating the semiconductor wafer into the plurality of semiconductor die, increasing spacing between the plurality of semiconductor die. The method can further include encapsulating, in a molding compound, the plurality of semiconductor die and determining respective locations of one or more alignment features disposed within the molding compound. The method can still further include forming, based on the determined respective locations, one or more alignment marks in the molding compound.

Abstract: A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.

Abstract: In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.

Abstract: An MRAM device includes a first conductive pattern including a material generating a spin orbital torque, a torque transfer pattern contacting a portion of an upper surface of the first conductive pattern, an insulation pattern on a side of the torque transfer pattern and covering the first conductive pattern, and a magnetic tunnel junction (MTJ) structure on the torque transfer pattern, the MTJ structure including a free layer pattern, a tunnel barrier pattern, and a fixed layer pattern sequentially stacked.

Abstract: The present disclosure relates to a method of manufacturing a semiconductor device, including the successive steps of: a) forming doped germanium on a germanium layer covering a first support; b) covering said doped germanium with a second support; and c) removing the first support.

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.

Abstract: Semiconductor devices and methods for forming the semiconductor devices include forming a sacrificial layer on a substrate on each side of a stack of nanosheets, the stack of nanosheets including first nanosheets and second nanosheets stacked in alternating fashion with a dummy gate structure formed thereon. Source and drain regions are grown on from the sacrificial layer and from ends of the second nanosheets to form source and drain regions in contact with each side of the stack of nanosheets. The sacrificial layer is removed. An interlevel dielectric is deposited around the source and drain regions to fill between the source and drain regions and the substrate.

Abstract: Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts.

Abstract: An electroluminescent display substrate and a manufacturing method thereof, a display panel and a display apparatus are disclosed. The electroluminescent display substrate includes: a base substrate including a display area and a peripheral area surrounding the display area, wherein at least one OLED device is in the display area; a pixel defining layer in the display area and the peripheral area; at least one groove in the pixel defining layer in the peripheral area; wherein the at least one OLED device has a first electrode, the first electrode is on a side of the pixel defining layer away from the base substrate and extends to cover the groove.

Abstract: A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has a N+ implant source region. In one embodiment, a JFET is provided with a drain metal deposited over a backside of an N substrate, an n-type drift layer epitaxial grown over a topside of the N substrate, a buried P-type block layer deposited over the n-type drift layer, an implanted N+ source region on side walls of the lateral channel layer, and an source metal attached to the top of the p-layer and attached to the implanted N+ source region at the side. In one embodiment, the JFET further comprises a gate layer, and wherein the gate layer is a dielectric gate structure that enables a fully enhanced channel. In another embodiment, the gate layer is a p-type GaN gate structure that enables a partially enhanced channel.

Abstract: A method is presented for reducing parasitic capacitance. The method includes forming a source region and a drain region within a substrate, forming spacers in direct contact with sidewalls of a sacrificial layer, depositing an inter-layer dielectric (ILD) over the source and drain regions, replacing the sacrificial layer with a gate structure, removing the ILD, and depositing a sacrificial dielectric layer. The method further includes removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions, depositing a conductive material over the exposed top surfaces of the source and drain regions, and removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions.

Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a second semiconductor fin, a gate structure, a shallow trench isolation (STI) oxide, and a dielectric layer. The first semiconductor fin and a second semiconductor fin extend upwardly from the substrate. The gate structure extends across the first and second semiconductor fins. The shallow trench isolation (STI) oxide has a horizontal portion extending along a top surface of the substrate and vertical portions extending upwardly from the horizontal portion along the first and second semiconductor fins. The dielectric layer has a horizontal portion extending along a top surface of the horizontal portion of the STI oxide and vertical portions extending upwardly from the horizontal portion of the dielectric layer to a position higher than top ends of the vertical portions of the STI oxide.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.