Patents Examined by Earl N. Taylor
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Patent number: 11171254Abstract: A method of producing a bifacial photovoltaic cell is disclosed herein, the method comprising: forming a boron-containing layer on a second surface of a semiconductor substrate; forming a cap layer above the boron-containing layer; effecting simultaneously: i) deposition on the first surface and ii) diffusion into it of the phosphorous using POCl3 gas phase process and iii) diffusion of the boron into the second surface of the substrate, to thereby dope the first surface with n-dopant and the second surface with boron.Type: GrantFiled: December 27, 2018Date of Patent: November 9, 2021Assignee: SOLAROUND LTD.Inventors: Naftali Paul Eisenberg, Lev Kreinin, Ygal Eisenberg
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Patent number: 11171172Abstract: A back side illumination (BSI) image sensor is provided. The BSI image sensor includes a semiconductor substrate, a first dielectric layer, a reflective element, a second dielectric layer and a color filter layer. The semiconductor substrate has a front side and a back side. The first dielectric layer is disposed on the front side of the semiconductor substrate. The reflective element is disposed on the first dielectric layer, in which the reflective element has an inner sidewall contacting the first dielectric layer, and the inner sidewall has a zigzag profile. The second dielectric layer is disposed on the first dielectric layer and the reflective element. The color filter layer is disposed on the backside of the semiconductor substrate.Type: GrantFiled: July 16, 2019Date of Patent: November 9, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Patent number: 11164981Abstract: A method includes depositing a first layer including amorphous silicon on a surface of a substrate; depositing a second layer including metal on the first layer; and performing an annealing process at a temperature within a range of 70° C. to 200° C., thereby inducing a silicidation reaction between the first layer and the second layer and forming a third layer comprising a metal silicide in electrical contact with the substrate, resulting in a remaining part of the first layer being between the substrate and the third layer.Type: GrantFiled: February 10, 2020Date of Patent: November 2, 2021Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT, KU LEUVEN R&DInventors: Jinyoun Cho, Maria Jesus Recaman Payo, Maarten Debucquoy, Jef Poortmans
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Patent number: 11158585Abstract: An integrated circuit package shield comprising a frame comprising two or more segments, the segments to interlock with one another along a substrate and the segments comprising electrically conductive material to electrically couple to the substrate; and a lid to cover the frame, the lid comprising a conductive material to electrically couple to the substrate.Type: GrantFiled: March 27, 2018Date of Patent: October 26, 2021Assignee: Intel IP CorporationInventor: Rizwan Fazil
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Patent number: 11158647Abstract: A memory device includes a semiconductor substrate, a logic transistor, and a storage transistor. The semiconductor substrate has a logic region and a memory region. The logic transistor is disposed on the logic region, in which the logic transistor comprises a high-k metal gate structure. The storage transistor is disposed on the memory region, in which the storage transistor includes a charge storage structure and a high-k metal gate structure. The charge storage structure is disposed on the memory region. The high-k metal gate structure is disposed on the charge storage structure.Type: GrantFiled: December 16, 2019Date of Patent: October 26, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun-Chi Wu, Chung-Jen Huang
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Patent number: 11152359Abstract: An integrated circuit device includes: a substrate including a fin type active region extending in a first direction; a gate structure intersecting the fin type active region and extending in a second direction perpendicular to the first direction; a source/drain region on sides of the gate structure; a gate isolation insulating layer contacting an end of the gate structure; a first contact connected to the source/drain region; and a second contact connected to the source/drain region, the second contact being longer in the second direction than the first contact, the second contact includes a first portion extending in the second direction from an area adjacent to one side of the gate structure beyond the end of the gate structure and facing a sidewall of the gate structure, and a second portion facing a sidewall of the gate isolation insulating layer, and the first portion is wider than the second portion.Type: GrantFiled: July 15, 2020Date of Patent: October 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeonglim Kim, Sunghwan Bae, Seulki Hong, Myungsoo Noh, Moongi Cho
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Patent number: 11145571Abstract: In one general aspect, an apparatus can include a substrate, a semiconductor die coupled with a first surface of the substrate, and a metal layer disposed on a second surface of the substrate. The second surface can be opposite the first surface. The apparatus can also include a plurality of metal fins coupled with the metal layer, and a metal ring coupled with the metal layer. The metal ring can surround the plurality of metal fins.Type: GrantFiled: July 16, 2019Date of Patent: October 12, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Inpil Yoo, Jerome Teysseyre, Seungwon Im, Dongwook Kang
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Patent number: 11145689Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chips and related methods are disclosed. LED chips are provided that include an indicia arranged between a primary light-emitting face and a mounting face of the LED chip. The indicia may include at least one of a logo, one or more alphanumeric characters, or a symbol, among others that are configured to convey information. Arrangements of at least one of an n-contact, a p-contact, or a reflector layer of the LED chip may form the indicia. LED chips are also provided where at least a portion of an indicia is arranged on a mounting face of the LED chip. Indicia are provided that may be visible through primary light-emitting faces when LED chips are electrically activated or electrically deactivated. In this regard, the indicia may be embedded within LED chips while still being able to convey information.Type: GrantFiled: November 29, 2018Date of Patent: October 12, 2021Assignee: CreeLED, Inc.Inventors: Nikolas Hall, Derek Miller, Anoop Mathew, Colin Blakely, Luis Breva, Jesse Reiherzer, David Todd Emerson
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Patent number: 11145591Abstract: An IC device includes an integrated capacitor and anti-fuse. Prior to programming of the anti-fuse, electrical current is configured to flow siloed between a first circuit element and a second circuit element through a first VIA. The anti-fuse may be programed by applying a fusing voltage to a second VIA to charge an anti-fuse plate. Within the anti-fuse, the anti-fuse plate is separated from the first capacitor plate by a dielectric. The fusing voltage causes an electric field between the plates to exceed a breakdown field strength of the dielectric which results in an electric arc between the anti-fuse plate and the capacitor plate. The electric arc fuses or otherwise joins the anti-fuse plate and the capacitor plate. Functionality of the IC device may be altered by allowing or driving current from the first circuit element or the second circuit element across the fused plates.Type: GrantFiled: November 18, 2019Date of Patent: October 12, 2021Assignee: International Business Machines CorporationInventors: Jim Shih-Chun Liang, Baozhen Li, Chih-Chao Yang
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Patent number: 11133223Abstract: A semiconductor device and a method of making the same are provided. A method according to the present disclosure includes providing a workpiece comprising a first source/drain region in a first device region and a second source/drain region in a second device region, depositing a dielectric layer over the first source/drain region and the second source drain region, forming a first via opening in the dielectric layer to expose the first source/drain region and a second via opening in the dielectric layer to expose the second source/drain region, annealing the workpiece to form a first semiconductor oxide feature over the exposed first source/drain region and a second semiconductor oxide feature over the exposed second source/drain region, removing the first semiconductor oxide feature to expose the first source/drain region in the first via opening in dielectric layer, and selectively forming a first epitaxial feature over the exposed first source/drain region.Type: GrantFiled: July 16, 2019Date of Patent: September 28, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ding-Kang Shih, Cheng-Long Chen, Pang-Yen Tsai
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Patent number: 11121258Abstract: A transistor comprising a channel region on a material is disclosed. The channel region comprises a two-dimensional material comprising opposing sidewalls and oriented perpendicular to the material. A gate dielectric is on the two-dimensional material and gates are on the gate dielectric. Semiconductor devices and systems including at least one transistor are disclosed, as well as methods of forming a semiconductor device.Type: GrantFiled: August 27, 2018Date of Patent: September 14, 2021Assignee: Micron Technology, Inc.Inventors: Witold Kula, Gurtej S. Sandhu, John A. Smythe
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Patent number: 11121129Abstract: Provided is a semiconductor device including a substrate, a gate structure, a first metal layer, and a gate via. The substrate has at least three semiconductor fins to define an active region. The gate structure is across the at least three semiconductor fins and extends along a first direction. The first metal layer extends along a second direction and is disposed over the gate structure. The gate via is disposed between the gate structure and the first metal layer. The gate via has a longitudinal axis extending along the first direction and across the first metal layer. A length of the longitudinal axis of the gate via is greater than a width of the first metal layer.Type: GrantFiled: October 18, 2018Date of Patent: September 14, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jhon-Jhy Liaw
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Patent number: 11121268Abstract: A semiconductor light-receiving element includes a substrate; a light-receiving mesa portion, formed on top of the substrate, including a first semiconductor layer of a first conductivity type, an absorption layer, and a second semiconductor layer of a second conductivity type; a light-receiving portion electrode, formed above the light-receiving mesa portion, connected to the first semiconductor layer; a pad electrode formed on top of the substrate; and a bridge electrode, placed so that an insulating gap is interposed between the bridge electrode and the second semiconductor layer, configured to connect the light-receiving portion electrode and the pad electrode on top of the substrate, the bridge electrode being formed in a layer separate from layers of the light-receiving portion electrode and the pad electrode.Type: GrantFiled: April 9, 2020Date of Patent: September 14, 2021Assignee: Lumentum Japan, Inc.Inventors: Ryu Washino, Hiroshi Hamada, Takafumi Taniguchi
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Patent number: 11107615Abstract: A magnetization rotational element includes a ferromagnetic metal layer, and a spin-orbit torque wiring extending in a first direction intersecting a lamination direction of the ferromagnetic metal layer and having the ferromagnetic metal layer positioned on one surface thereof, in which a direction of spin injected from the spin-orbit torque wiring into the ferromagnetic metal layer intersects a magnetization direction of the ferromagnetic metal layer, and a damping constant of the ferromagnetic metal layer is larger than 0.01.Type: GrantFiled: February 22, 2018Date of Patent: August 31, 2021Assignee: TDK CORPORATIONInventors: Tohru Oikawa, Tomoyuki Sasaki, Yohei Shiokawa, Tatsuo Shibata
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Patent number: 11088180Abstract: The present disclosure provides a conductive wire structure, a manufacturing method thereof, an array substrate and a display device. The conductive wire structure includes a first conductive wire and a second conductive wire on a first plane, wherein a connection end of the first conductive wire is spaced apart from a connection end of the second conductive wire by a gap so as to discharge charges accumulated on the first conductive wire and the second conductive wire through the gap; an electrical connector connected to the connection end of the first conductive wire and the connection end of the second conductive wire, respectively, wherein a part of the electrical connector is located on a second plane different from the first plane.Type: GrantFiled: July 16, 2019Date of Patent: August 10, 2021Assignees: Hefei BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Tianzhen Liu, Xianxue Duan, Dezhi Xu
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Patent number: 11081615Abstract: A protection method for through-holes of a semiconductor wafer having the steps: providing a semiconductor wafer, and comprising a plurality of solar cell stacks, wherein each solar cell stack has a Ge substrate forming a bottom side of the semiconductor wafer, a Ge subcell, and at least two III-V subcells in the order mentioned, as well as at least one through-hole, extending from the top side to the bottom side of the semiconductor wafer, with a continuous side wall and a circumference that is oval in cross section; applying a photoresist layer to a top side of the semiconductor wafer and to at least one region of the side wall of the through-hole, said region adjoining the top side, and applying an organic filler material by means of a printing process to a region of the top side, said region comprising the through-hole, and into the through-hole.Type: GrantFiled: August 31, 2020Date of Patent: August 3, 2021Assignee: AZUR SPACE Solar Power GmbHInventors: Alexander Frey, Benjamin Hagedorn
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Patent number: 11069824Abstract: An optical sensor device has an optical semiconductor element fixed into a recessed portion of a base portion, and a pad portion of the optical semiconductor element is electrically connected to a lead portion of the base portion. On an upper surface of a protruding portion provided in an outer region of the base portion, a metallization layer having notch portions, a metal bonding layer, a metallization layer having notch portions, and a lid portion are provided. Through use of the metallization layers and the metal bonding layer, the lid portion can be hermetically bonded to the base portion.Type: GrantFiled: January 31, 2020Date of Patent: July 20, 2021Assignee: ABLIC INC.Inventor: Koji Tsukagoshi
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Patent number: 11063169Abstract: The present disclosure relates to methods and apparatus for structuring a semiconductor substrate. In one embodiment, a method of substrate structuring includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portions of the resist layer are then transferred onto the substrate by micro-blasting to form desired features in the substrate while unexposed or un-ablated portions of the resist layer shield the rest of the substrate. The substrate is then exposed to an etch process and a de-bonding process to remove the resist layer and release the carrier.Type: GrantFiled: November 18, 2019Date of Patent: July 13, 2021Assignee: Applied Materials, Inc.Inventors: Han-Wen Chen, Steven Verhaverbeke, Giback Park
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Patent number: 11062951Abstract: A process for fabricating a field-effect transistor includes providing a structure including a first silicon layer and a second layer, made of SiGe alloy, covering the first silicon layer. The method further includes forming a sacrificial gate covered with a hardmask on top of the second layer made of SiGe alloy and etching the second layer made of SiGe alloy, following the pattern of the hardmask in order to delimit an element made of SiGe alloy in the second layer. The method also includes forming spacers on top of the first silicon layer on either side of the sacrificial gate and of the element, removing the sacrificial gate, and enriching the first layer arranged beneath the element in germanium using a germanium condensation process.Type: GrantFiled: November 13, 2019Date of Patent: July 13, 2021Assignee: Commissariat A L'Energie Atomique et aux Energies AlternativesInventor: Shay Reboh
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Patent number: 11063055Abstract: A second gate dielectric film material and a memory gate electrode material are formed on a semiconductor substrate. The memory gate electrode material and the second gate dielectric film material formed in a peripheral circuit forming region are removed, and a part of each of the memory gate electrode material and the second gate dielectric film material is left in the memory cell forming region. Thereafter, in a state that the semiconductor substrate in the memory cell forming region is covered with a part of each of the memory gate electrode material and the second gate dielectric film material, heat treatment is performed to the semiconductor substrate to form a third gate dielectric film on the semiconductor substrate located in the peripheral circuit forming region. Thereafter, a memory gate electrode and a second gate dielectric film are formed.Type: GrantFiled: November 6, 2019Date of Patent: July 13, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yoshiyuki Kawashima