Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.

Abstract: The present disclosure provides a photo sensing device, the photo sensing device includes a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, and a composite layer disposed between the photosensitive member and the silicon layer and surrounding the photosensitive member, wherein the composite layer includes a first material and a second material different from the first material.

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanostructure channels and NMOS transistors comprising silicon nanostructure channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanostructure channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanostructure channels for NMOS transistors. PMOS transistors having germanium nanostructure channels and NMOS transistors having silicon nanostructure channels are formed as part of a single fabrication process.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a first gate structure over and wrapping around each of the first plurality of channel members, a second gate structure over and wrapping around each of the second plurality of channel members, and a through-substrate contact that extends between the first plurality of channel members and the second plurality of channel members, between the first gate structure and the second gate structure, and through the backside dielectric layer.

Abstract: The present disclosure provides a photo sensing device, the photo sensing device includes a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, and a superlattice layer disposed between the photosensitive member and the silicon layer, wherein the superlattice layer includes a first material and a second material different from the first material, a first concentration of the second material at a portion of the superlattice layer proximal to the photosensitive member is greater than a second concentration of the second material at a portion of the superlattice layer distal to the photosensitive member.

Abstract: A photodetector is provided. The photodetector includes a semiconductor layer, a first superlattice structure in the semiconductor layer, and a light absorption material above the first superlattice structure. The first superlattice structure includes vertically stacked pairs of silicon layer/first silicon germanium layer. The first silicon germanium layers are made of Si1-xGex, and x is the atomic percentage of germanium and 0.1?x?0.9.

Abstract: The application discloses a light-emitting device including a carrier, a light-emitting element and a connecting structure. The carrier includes a first connecting portion and a first necking portion extended from the first connecting portion. The first connecting portion has a first width, and the first necking portion has a second width. The second width is less than the first width. The light-emitting element includes a first light-emitting layer being able to emit a first light and a first contacting electrode formed under the first light-emitting layer. The first contacting electrode is corresponded to the first connecting portion. The connecting structure includes a first electrical connecting portion and a protecting portion surrounding the first electrical connecting portion. The first electrical connecting portion is electrically connected to the first connecting portion and the first contacting electrode.

Abstract: A dicing method for separating a wafer comprising a plurality of solar cells stack along at least one parting line, at least having the steps of: providing the wafer with a top, a bottom, an adhesive layer which is integrally bonded with the top and a cover glass layer which is integrally bonded with the adhesive layer, wherein the wafer includes a plurality of solar cell stacks, each having a germanium substrate layer forming the bottom of the wafer, a germanium sub-cell and at least two III-V sub-cells; creating a separating trench along the parting line by means of laser ablation, which extends from a bottom of the wafer through the wafer and the adhesive layer at least up to a top of the cover glass layer; and dividing the cover glass layer along the separating trench.

Abstract: Methods of fabricating solar cells using UV-curing of light-receiving surfaces of the solar cells, and the resulting solar cells, are described herein. In an example, a method of fabricating a solar cell includes forming a passivating dielectric layer on a light-receiving surface of a silicon substrate. The method also includes forming an anti-reflective coating (ARC) layer below the passivating dielectric layer. The method also includes exposing the ARC layer to ultra-violet (UV) radiation. The method also includes, subsequent to exposing the ARC layer to ultra-violet (UV) radiation, thermally annealing the ARC layer.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.

Abstract: The present disclosure relates to methods and apparatus for structuring a semiconductor substrate. In one embodiment, a method of substrate structuring includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portions of the resist layer are then transferred onto the substrate by micro-blasting to form desired features in the substrate while unexposed or un-ablated portions of the resist layer shield the rest of the substrate. The substrate is then exposed to an etch process and a de-bonding process to remove the resist layer and release the carrier.

Abstract: A photodetection film includes a photodetection transistor. The photodetection transistor includes a gate electrode, a gate insulating layer surroundingly formed on the gate electrode, at least one drain terminal disposed on the gate insulating layer and is spaced apart from the gate electrode, at least one source terminal disposed on the gate insulating layer and is spaced apart from the gate electrode and the at least one drain terminal, and a light-absorbing semiconductor layer disposed on the gate insulating layer and extends between the drain and source terminals. A photodetection sensor, a photodetection display apparatus, and a method of making the photodetection film are also disclosed.

Abstract: A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.

Abstract: A display device according to the present invention includes a display region arranged with a plurality of pixels, and a sealing layer covering the display region, wherein the sealing layer includes an insulation layer having a density pattern, the density pattern is a pattern including a low density region and a high density region, the low density region has the insulation layer with a lower density than an average density within the display region of the insulation layer, and the high density region has the insulation layer with a higher density than an average density within the display region of the insulation layer.

Abstract: A multijunction solar cell includes a base substrate comprising a Group IV semiconductor and a dopant of a first carrier type. A patterned emitter is formed at a first surface of the base substrate. The patterned emitter comprises a plurality of well regions doped with a dopant of a second carrier type in the Group IV semiconductor. The base substrate including the patterned emitter form a first solar subcell. The multijunction solar cell further comprises an upper structure comprising one or more additional solar subcells over the first solar subcell. Methods of making a multijunction solar cell are also described.

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

Abstract: A method for making field effect transistors includes forming a connection leading out a gate structure arranged on one of a plurality of fins, and connections for source and drain and the gate structure are located on formation areas of different fins; forming a gate cap layer at the top of the gate structure to protect it on the same fin body and adjacent to the connections for source and drain; forming buried holes on the source and drain at both sides of the gate structure connection; forming a buried hole cap layer on the buried holes, to protect the buried holes which connect the source and the drain electrodes.

Abstract: A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.

Abstract: Method and structural embodiments are described which provide an integrated structure using polysilicon material having different optical properties in different regions of the structure.