Abstract: A liquid crystal display device having an outer shape of a display region formed other than a rectangle. A driver for supplying a video signal is disposed outside the display region. A selector with selector TFT is disposed between the display region and the driver. A video signal line is disposed between the driver and the selector, and a drain line is disposed between the selector and the display region. A scanning circuit for supplying a scanning signal to the scanning line is disposed outside the display region. The selector is disposed between the scanning line and the display region, and covered with ITO as the common electrode. The common bus wiring is disposed outside the selector.

Abstract: A display apparatus includes a substrate; a light-emitting diode on the substrate; a pixel separating layer surrounding the light-emitting diode; and a light dispersion layer on the light-emitting diode and the pixel separating layer.

Abstract: A semiconductor device includes a semiconductor layer with a thickness of at most 50 ?m. A first metallization structure is disposed on a first surface of the semiconductor layer. The first metallization structure includes a first copper region with a first thickness. A second metallization structure is disposed on a second surface of the semiconductor layer opposite to the first surface. The second metallization structure includes a second copper region with a second thickness. The total thickness, which is the sum of the first thickness and the second thickness, deviates from the thickness of the semiconductor layer by not more than 20% and a difference between the first thickness and the second thickness is not more than 20% of the total thickness.

Abstract: A semiconductor package includes: a core structure having first and second surfaces and having first and second through-holes; a first semiconductor chip embedded in the core structure and having first and second contacts disposed on two opposing surfaces thereof, respectively; a first wiring layer on the surface of the core structure and connected to the first contact; a second wiring layer on the second surface of the core structure and connected to the second contact; a chip antenna disposed in the first through-hole; a second semiconductor chip in the second through-hole and having a connection pad; a first redistribution layer on the first surface of the core structure and connected to the connection terminal, the connection pad, and the first wiring layer; an encapsulant encapsulating the chip antenna and the second semiconductor chip; and a second redistribution layer on the encapsulant connecting to the second wiring layer.

Abstract: An integrated circuit device includes a substrate, a fin field-effect transistor (FinFET), and a well strap. The substrate has a first doped region of a first type dopant. The FinFET is over the doped region and includes a first semiconductor fin and a first source/drain region in the first semiconductor fin, in which the first source/drain region is of a second type dopant that has a different conductivity type than the first type dopant. The well strap is over the doped region, includes a second semiconductor fin and a second source/drain region in the second semiconductor fin, in which the second source/drain region is of the first type dopant. A width of the second semiconductor fin is greater than a width of the first semiconductor fin.

Abstract: A method of forming a semiconductor structure includes providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion. The substrate further comprises a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface. A buffer layer is deposited in one or more of the plurality of grooves. A semiconductor material is epitaxially grown over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase.

Abstract: Provided is a resistance variation element including a resistance variation film of a metal depositing type, a first electrode which contacts with a first surface of the resistance variation film in a predetermined first region and supplies metallic ions via the first region, and a second electrode laminated on a second surface of the resistance variation film. The first region includes a recessed region surrounded by a simple closed curve or a region surrounded by a plurality of simple closed curves. A line segment which passes through a point outside of the first region, ends of which exist on the simple closed curve, and each point of which in the vicinity of both the ends other than both the ends is outside of the first region, exists, and an edge of the first electrode is formed in a part of the simple closed curve including both the ends.

Abstract: Disclosed is a substrate treating method for performing a heat treatment of a substrate having a treated film formed thereon in a heat treating space of a heat treating chamber. The method includes an exhaust step of performing exhaust of gas within the heat treating space, an inert gas supply step of supplying inert gas into the heat treating space, and a heat treating step of performing the heat treatment of the substrate in the heat treating space.

Abstract: A micro semiconductor structure is provided. The micro semiconductor structure includes a substrate, at least one supporting layer, and at least one micro semiconductor device. The supporting layer includes at least one upper portion and a bottom portion, wherein the upper portion extends in a first direction. The length L1 of the upper portion in the first direction is greater than the length L2 of the bottom portion in the first direction. Furthermore, the bottom surface of the micro semiconductor device is in direct contact with the upper portion of the supporting layer.

Abstract: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.

Abstract: A semiconductor device herein includes doped extension regions for silicon and silicon germanium nanowires. The nanowires can be selectively grown and recessed into a gate spacer. The semiconductor device can include a gate structure including the gate spacer; the nanowire or channel extending through the gate structure such that an end of the channel is recessed within a recess in said gate spacer; an extension region in contact with the end of the channel within the recess, the extension region being formed of an extension material having a different composition than a channel material of the channel such that a strain is provided in the channel; and a source-drain contact in contact with the extension region and adjacent to the gate structure.

Abstract: An integrated circuit assembly having an improved solder connection, and methods for fabricating the same are provided that utilize platelets within the solder connections to inhibit solder connection failure, thus providing a more robust solder interface. In one example, an integrated circuit assembly is provided that includes a package substrate having a first plurality of contact pads exposed on a first surface of the package substrate and a second plurality of contact pads exposed on a second surface of the package substrate. The second plurality of contact pads have a pitch that is greater than a pitch of the first plurality of contact pads. Interconnect circuitry is disposed in the package substrate and couples the first and second pluralities of contact pads. At least a first contact pad of the second plurality of contact pads includes a solder ball disposed directly in contact with a palladium layer.

Abstract: Disclosed is a substrate treating method for treating a substrate with a directed self-assembly material applied thereto. The substrate treating method includes a heating step and a cooling step. The heating step includes heating the substrate to perform phase separation of the directed self-assembly material by maintaining an interior of a treatment container in a non-oxidizing gas atmosphere and placing the substrate at a heating position. The cooling step includes cooling the substrate by maintaining the interior of the treatment container in the non-oxidizing gas atmosphere, placing the substrate at a cooling position further away from the heating unit than the heating position, supplying non-oxidizing gas into the treatment container, and exhausting gas within the treatment container.

Abstract: Disclosed is a substrate treating method for performing a heat treatment of a substrate in a heat treating space. The method includes a loading step of loading the substrate on support pins, an exhaust step of exhausting gas within the heat treating space, an inert gas supply step of supplying inert gas into the heat treating space, an under-substrate space gas discharging step of discharging gas within an under-substrate space between the substrate and the top face of the heat treating plate, and a heat treating step of retracting the support pins into the heat treating plate, and performing the heat treatment of the substrate placed on the top face of the heat treating plate in the heat treating space.

Abstract: A sensing device includes a first III-V compound stack and a second III-V compound stack. The first III-V compound stack has a first sensing area, and the second III-V compound stack has a second sensing area. A passivation layer fully covers the second sensing area. The first III-V compound stack is physically separated from the second III-V compound stack, and has material compositions and structures same as the second III-V compound stack.

Abstract: MEMS structures and methods utilizing a locker film are provided. In an embodiment a locker film is utilized to hold and support a moveable mass region during the release of the moveable mass region from a surrounding substrate. By providing additional support during the release of the moveable mass, the locker film can reduce the amount of undesired movement that can occur during the release of the moveable mass, and preventing undesired etching of the sidewalls of the moveable mass.

Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.

Abstract: A method for producing an optoelectronic device is disclosed. The method include preforming an inductive excitation of a current by an inductive component of the optoelectronic device such that the optoelectronic device emits electromagnetic radiation, measuring of at least one electro-optical characteristic of the optoelectronic device and applying a converter material to an emission side of the optoelectronic device, wherein a quantity of the converter material is determined from the measurement of the electro-optical characteristic.

Abstract: A semiconductor device includes a substrate, a core device disposed above the substrate, and an input/output (I/O) device disposed above the substrate. The core device includes a first gate electrode having a bottom surface and a sidewall that define a first interior angle therebetween. The first interior angle is an obtuse angle. The I/O device includes a second gate electrode having a bottom surface and a sidewall that define a second interior angle therebetween. The second interior angle is greater than the first interior angle.

Abstract: A semiconductor component includes a substrate having a dense zone and a less-dense zone, at least one first FinFET device disposed on the dense zone, and at least one second FinFET device disposed on the less-dense zone, in which a width of a first source/drain region of the first FinFET device is smaller than a width of a second source/drain region of the second FinFET device.