Abstract: A method of forming an array of capacitors comprises forming a vertical stack above a substrate. The stack comprises a horizontally-elongated conductive structure and an insulator material directly above the conductive structure. Horizontally-spaced openings are formed in the insulator material to the conductive structure. An upwardly-open container-shaped bottom capacitor electrode is formed in individual of the openings. The bottom capacitor electrode is directly against conductive material of the conductive structure. The conductive structure directly electrically couples the bottom capacitor electrodes together. A capacitor insulator is formed in the openings laterally-inward of the bottom capacitor electrodes. A top capacitor electrode is formed in individual of the openings laterally-inward of the capacitor insulator. The top capacitor electrodes are not directly electrically coupled together. Structure independent of method is disclosed.

Abstract: A display device can include a pixel driver disposed on a substrate; and a display element electrically connected with the pixel driver, in which the pixel driver includes a first thin film including a first semiconductor layer, a first gate electrode, at least a part of the first gate electrode overlapping with the first semiconductor layer, and a first source electrode and a first drain electrode respectively connected with the first semiconductor layer; and a second thin film including a second semiconductor layer, a second gate electrode, at least a part of the second gate electrode overlapping with the second semiconductor layer, and a second source electrode and a second drain electrode respectively connected with the second semiconductor layer, in which the first semiconductor layer and the second semiconductor layer are disposed in different layers, and the first source electrode, the first drain electrode, the second gate electrode, the second source electrode, and the second drain electrode are disp

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

Abstract: A semiconductor device includes fins extending substantially parallel to a first direction, at least one of the fins being a dummy fin; and at least one of the fins being an active fin; and at least one gate structure formed over corresponding ones of the fins and extending substantially parallel to a second direction, the second direction being substantially perpendicular to the first direction; wherein the fins and the at least one gate structure are located in a cell region which includes an odd number of fins. In an embodiment, the cell region is substantially rectangular and has first and second edges which are substantially parallel to the first direction; and neither of the first and second edges overlaps any of the fins.

Abstract: A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset.

Abstract: A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.

Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

Abstract: An LED light source is described herein, which comprises: a hollow heat sink having a top wall, a bottom opening, and a sidewall, the top wall including an upper surface and a lower surface, the upper surface having a central area and a peripheral area, and the top wall having at least one first hole in the peripheral area; an interposer being overmolded on the peripheral area and the lower surface, and extending through the at least one first hole; an LED package comprising at least one LED chip and mounted in the central area; an LED driver located within the hollow heat sink and positioned on a side of the interposer facing the bottom opening.

Abstract: A method for manufacturing a ray detector array substrate is provided, comprising: forming a thin film transistor, a first data line and a receiving electrode on a base substrate; forming a first passivation layer on the base substrate; forming a first via hole and a second via hole in regions of the first passivation layer corresponding to the first data line and the receiving electrode, respectively; forming a photoelectric conversion layer covering the first passivation layer on the base substrate, the first via hole and the second via hole being filled with a material of the photoelectric conversion layer; etching the photoelectric conversion layer to retain a first portion of the photoelectric conversion layer inside the first via hole, and a second portion of the photoelectric conversion layer above and corresponding to the second via hole.

Abstract: An optical device (30) includes a light-emitting device (10) and a sensor device (20) (light-receiving element (220)). The light-emitting device (10) includes a substrate (100), a plurality of light-emitting portions (140), and light-transmitting portions (106). The light-emitting portions (140) are located at a first surface (100a) side of the substrate (100). The light-emitting portion (140) has a light-shielding portion (102: first light-shielding portion). The light-shielding portion (102) is located at a position to cover light emitted from the adjacent light-emitting portion (140: first light-emitting portion) and emitted to the first surface (100a) side at at least any angle between 70° to 90° from the light-emitting device (10).

Abstract: A substrate treating method for performing a heat treatment of a substrate that has a treated film formed thereon in a heat treating space of a heat treating chamber. The method includes an exhaust step of exhausting gas within the heat treating space formed by a cover enclosing surroundings of a heat treating plate; an inert gas supply step of supplying inert gas from an upper portion of the heat treating space into the heat treating space and supplying inert gas into a gap between an outer peripheral surface of the heat treating plate and an inner wall of the cover; and a heat treating step of performing the heat treatment of the substrate in the heat treating space. The heat treating step is performed after the exhaust step and the inert gas supply step.

Abstract: A void-less bottom electrode structure is formed at least partially in a via opening having a small feature size and containing a conductive landing pad structure which is composed of a metal-containing seed layer that is subjected to a reflow anneal. A metal-containing structure is located on a topmost surface of the bottom electrode structure. The metal-containing structure may be composed of an electrically conductive metal-containing material or a material stack of electrically conductive metal-containing materials. In some embodiments, the bottom electrode and the metal-containing structure collectively provide a non-volatile memory device.

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site.

Abstract: An manufacturing method of a display device may include the following steps: forming a transistor on a substrate; forming an insulating layer on the transistor; forming a conductive layer including silver on the insulating layer; forming a photosensitive member on the conductive layer; forming an electrode of a light-emitting element by etching the conductive layer; performing plasma treatment on a structure that comprises the electrode, the plasma treatment using a gas including a halogen; and removing a product that is resulted from the plasma treatment.

Abstract: A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first magnetic tunnel junction stack. The first magnetic tunnel junction stack includes a first reference layer. The method also includes forming a second magnetic tunnel junction stack, where the second magnetic tunnel junction stack includes a second reference layer. The method also includes bonding the first magnetic tunnel junction stack to the second magnetic tunnel junction stack with ultra-high vacuum bonding to form the double magnetic tunnel junction device.

Abstract: A semiconductor device includes: channel patterns disposed on a substrate; a pair of source/drain patterns disposed at first and second sides of each of the channel patterns; and a gate electrode disposed around the channel patterns, wherein the gate electrode includes a first recessed top surface between adjacent channel patterns, wherein the channel patterns are spaced apart from the substrate, and wherein the gate electrode is disposed between the substrate and the channel patterns.

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate structure over the substrate. The gate structure includes a high-k layer over the substrate, a shielding layer over the high-k layer, and an N-type work function metal layer over the shielding layer. In some embodiments, the shielding layer has a dielectric constant less than a dielectric constant of the high-k layer.

Abstract: According to one embodiment, a plasma processing apparatus includes a processing chamber, a sample stage that is disposed inside the processing chamber and electrically divided into a plurality of regions on which a sample is placed, an electromagnetic wave introduction unit that introduces electromagnetic waves into the processing chamber, and a bias power applying unit that applies bias power to the sample stage, in which the bias power applying unit is configured to include a first radio frequency power applying unit that applies first radio frequency power to a first region out of the plurality of electrically divided regions of the sample stage, a second radio frequency power applying unit that applies second radio frequency power to a second region out of the plurality of electrically divided regions of the sample stage, and a phase adjuster that controls the first radio frequency power applying unit and the second radio frequency power applying unit to shift the phases of the first radio frequency powe

Abstract: A MTJ stack is deposited on a bottom electrode. A metal hard mask is deposited on the MTJ stack and a dielectric mask is deposited on the metal hard mask. A photoresist pattern is formed on the dielectric mask, having a critical dimension of more than about 65 nm. The dielectric and metal hard masks are etched wherein the photoresist pattern is removed. The dielectric and metal hard masks are trimmed to reduce their critical dimension to 10-60 nm and to reduce sidewall surface roughness. The dielectric and metal hard masks and the MTJ stack are etched wherein the dielectric mask is removed and a MTJ device is formed having a small critical dimension of 10-60 nm, and having further reduced sidewall surface roughness.

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. In one form, a method for forming a semiconductor structure includes: providing a base; forming multiple spaced filling layers in the base; etching the base to form multiple independent fin portions; and etching the filling layers to form multiple independent pseudofin portions. In one form a semiconductor structure of the present disclosure includes: a substrate, multiple independent fin portions and multiple independent pseudofin portions, wherein the substrate includes device areas, and isolating areas located between the device areas; the multiple independent fin portions are located on the substrate in the device areas and are the same with the substrate in material; and the multiple independent pseudofin portions are located on the substrate in the isolating areas and are different from the substrate in material.