Abstract: At an upper surface of a gate electrode, a recess occurs due to etching back of poly-silicon for forming the gate electrode. At an upper surface of an interlayer insulating film, a recess occurs in a portion that opposes in a depth direction, the recess of the upper surface of the gate electrode. A barrier metal includes sequentially stacked first to fourth metal films. The first metal film is a titanium nitride film that covers the surface of the interlayer insulating film and has an opening that exposes the recess of the upper surface of the interlayer insulating film. The second metal film is a titanium film that covers the first metal film and the source electrode, and is in contact with the interlayer insulating film, in the opening of the first metal film. The third and fourth metal films are a titanium nitride film and a titanium film, respectively.

Abstract: A high voltage thin-film transistor is specified comprising a gate electrode (G11, G21) in a gate electrode layer (31), a semiconductive channel (C11,C12) in a channel layer (34) parallel to the gate electrode layer and being electrically insulated from the gate electrode by a gate dielectric layer (32). The transistor further comprises a dominant main electrode and a subordinate main electrode (M11, M12). The main electrodes each have an external portion (M11e, M12e) in a main electrode layer (36) and an internal portion (M11e, M12e) that protrudes through a further dielectric layer (35) between the main electrode layer and the channel layer to electrically contact the semiconductive channel in a dominant main electrode contact area (M11c) and a subordinate main electrode contact area (M12c) respectively.

Abstract: A semiconductor component including: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film.

Abstract: A semiconductor memory device is provided. The device includes a substrate including a cell region and a peripheral region; a plurality of lower electrodes disposed on the substrate in the cell region; a dielectric layer disposed on the plurality of lower electrodes; a metal containing layer disposed on the dielectric layer; a silicon germanium layer disposed on and electrically connected to the metal containing layer; a conductive pad disposed on and electrically connected to the silicon germanium layer; and an upper electrode contact plug disposed on and electrically connected to the conductive pad; The conductive pad extends from the upper electrode contact plug towards the peripheral region in a first direction, and the silicon germanium layer includes an edge portion that extends past the conductive pad in the first direction.

Abstract: In one or more embodiments, a high impedance surface (HIS) apparatus comprises a core; a first set of conducting pads, where a first side of the first set of conducting pads is connected to a first side of the core; and a second set of conducting pads, where a first side of the second set of conducting pads is connected to a second side of the core. The apparatus further comprises a plurality of chip inductors, where at least a portion of the chip inductors are connected to a second side of the first set of conducting pads; and a plurality of chip capacitors, where at least a portion of the chip capacitors are connected to a second side of the second set of conducting pads.

Abstract: A method for predicting yield for a semiconductor process. A particular type of wafer is fabricated to have a first set of features disposed on the wafer, with a wafer map identifying a location for each of the first set of features on the wafer. Data from wafer acceptance tests and circuit probe tests is collected over time for wafers of that particular type as made in a semiconductor fabrication process, and at least one training dataset and a least one validation dataset are created from the collected data. A second set of “engineered” features are created and also incorporated onto the wafer and wafer map. Important features from the first and second sets of features are identified and selected, and using those important features as inputs, a number of different process models are run, with yield as the target. The results of the different models can be combined, for example, statistically.

Abstract: A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed.

Abstract: A light emitting device includes a first pixel that includes a first light-emitting structure, a first color conversion layer on the first light-emitting structure, and a first multi-layered filter on the first color conversion layer, and a second pixel that includes a second light-emitting structure, a second color conversion layer on the second light-emitting structure, and a second multi-layered filter on the second color conversion layer. Each of the first and second multi-layered filters includes at least one stack including a first film and a second film. The first multi-layered filter outputs light of a wavelength band that is different from a wavelength band of light output from the second multi-layered filter. The first multi-layered filter reflects light not output back into the first pixel and the second multi-layered filter reflects light not output back into the second pixel.

Abstract: An electroluminescent display device comprises a substrate; a plurality of sub-pixels arranged on the substrate, including sub-pixels with different colors arranged along a first direction and sub-pixels with a same color arranged along a second direction; a light-emitting diode disposed at each sub-pixel and including a first electrode, a light-emitting layer and a second electrode; a bank having an opening corresponding to a sub-pixel row along the second direction and disposed between two adjacent sub-pixels along the first direction; and a control pattern between two adjacent sub-pixels along the second direction, wherein the control pattern includes a first control pattern corresponding to a center portion of the sub-pixel row and a second control pattern spaced apart from the first control pattern along the second direction, and where a first end of each of the first and second control patterns is spaced apart from the bank and has an first surface parallel to or inclined with respect to the second dire

Abstract: A method of making a semiconductor package includes bonding a carrier to a surface of the substrate, wherein the carrier is free of active devices, wherein the carrier includes a carrier bond pad on a surface of the carrier. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad, wherein the bonding of the wafer bond pad to the carrier bond pad comprises re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad.

Abstract: A semiconductor device manufacturing method includes: forming an electrode including an Ni layer and an Au layer successively stacked on a semiconductor layer; forming a Ni oxide film by performing heat treatment to the electrode at a temperature of 350° C. or more to deposit Ni at least at a part of a surface of the Au layer and to oxidize the deposited Ni; and forming an insulating film in contact with the Ni oxide film and containing Si.

Abstract: Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.

Abstract: A semiconductor layer is etched into a plurality of fin structures. A first nitridation process is performed to side surfaces of the fin structures. The first nitridation process forms a first oxynitride layer at the side surfaces of the fin structures. A liner oxide layer is formed on the first oxynitride layer. An isolation structure is formed around the fin structures after the forming of the liner oxide layer.

Abstract: A high electron mobility transistor (HEMT) device and a method of forming the same are provided. The method includes forming a first III-V compound layer over a substrate. A second III-V compound layer is formed over the first III-V compound layer. The second III-V compound layer has a greater band gap than the first III-V compound layer. A third III-V compound layer is formed over the second III-V compound layer. The third III-V compound layer and the first III-V compound layer comprise a same III-V compound. A passivation layer is formed along a topmost surface and sidewalls of the third III-V compound layer. A fourth III-V compound layer is formed over the second III-V compound layer. The fourth III-V compound layer has a greater band gap than the first III-V compound layer.

Abstract: Techniques herein include systems and methods for fine control of temperature distribution across a substrate. Such techniques can be used to provide uniform spatial temperature distribution, or a biased spatial temperature distribution to improve plasma processing of substrates and/or correct characteristics of a given substrate. Embodiments include a plasma processing system with temperature control. Temperature control systems herein include a primary heating mechanism to heat a substrate, and a secondary heating mechanism that precisely modifies spatial temperature distribution across a substrate being processed. At least one heating mechanism includes a digital projection system configured to project a pattern of electromagnetic radiation onto or into a substrate, or through the substrate and onto a substrate support assembly.

Abstract: A chalcogenide material and an electronic device are provided. The chalcogenide material may include 1-10 atomic percent (at %) of silicon, 10-20 at % of germanium, 25-35 at % of arsenic, 40-50 at % of selenium, and 1-10 at % of tellurium. The electronic device may include a switching element including a chalcogenide material, the chalcogenide material including 1-10 atomic percent (at %) of silicon, 10-20 at % of germanium, 25-35 at % of arsenic, 40-50 at % of selenium, and 1-10 at % of tellurium. The electronic device may further include a first electrode electrically coupled to the switching element and a second electrode electrically coupled to the switching element.

Abstract: The invention relates to a power module. The power module has at least one power semiconductor and at least one further electronic component. The power module has a housing which is formed by a shaped body and is formed by an encapsulation compound. According to the invention, the housing is formed in at least two levels. At least one power semiconductor component is arranged in a first level and the at least one further electronic component is arranged in the second level. At least one electrically conductive layer, which forms an electrically conductive connecting structure, is formed on a surface of an inner boundary of the power module which extends between the levels. The connecting structure is applied directly to the surface. The at least one further electronic component is electrically conductively connected, in particular soldered or sintered, to the wiring structure.

Abstract: A phase module for a power converter includes first and second busbars and at least two semiconductor modules. The first busbar is connected to AC voltage connections of the semiconductor modules. The second busbar is connected to DC voltage connections of the semiconductor modules. At least one section of the first and second busbars is arranged at a distance to one another, the value of which is less than half the value of the distance between the AC voltage connection and the DC voltage connection of one of the semiconductor modules. At least one of the busbars has a separator arranged at a right angle on the remaining part of the busbar and connecting the busbar to at least one of the DC voltage connections or one of the AC voltage connections of one of the semiconductor modules. The separator is arranged along a surface of the one semiconductor module.

Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. The method includes forming a first active semiconductor region disposed in a first vertical level of the semiconductor structure, forming a second active semiconductor region disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction, forming a first conductive structure disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region.

Abstract: A semiconductor device includes a peripheral circuit area disposed on a first substrate and including circuit devices. A memory cell area is disposed on a second substrate and includes memory cells. A through wiring area includes a through contact plug and an insulating area. The through contact plug extends through the memory cell area and the second substrate and connects the memory cell area to the circuit devices. The insulating area surrounds the through contact plug. The insulating area includes a first insulating layer penetrating through the second substrate, a plurality of second insulating layers, a third insulating layer having a vertical extension portion, and a plurality of horizontal extension portions extended in parallel to a top surface of the second substrate from a side surface of the vertical extension portion to contact the second insulating layers.