Abstract: A system for computer memory management that implements a memory pool table, the memory pool table including entries that describe a plurality of memory pools, each memory pool representing a group of memory pages related by common attributes; a per-page tracking table, each entry in the per-page tracking table used to related a memory page with a memory pool of the memory pool table; and processing circuitry to: scan each entry in the per-page tracking table and, for each entry: determine an amount of memory released if the memory page related with the entry is swapped; aggregate the amount of memory for the respective memory pool related with the memory page related with the entry in the per-page tracking table, to produce a per-pool memory aggregate; and output the per-pool memory aggregate for the memory pools related with the memory pages in the per-page tracking table.

Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.

Abstract: Embodiments of the disclosure provide a method and an apparatus for accessing private data in a physical memory of an electronic device, wherein the method includes: receiving a request for accessing private data in the physical memory from a process running in the electronic device; and accessing private data in a particular physical address interval of the physical memory through a secure memory access interface added to a virtual machine monitor of the electronic device, wherein a mapping relationship for the particular physical address interval is not established in a memory management unit of the electronic device, and the secure memory access interface is pre-designed to realize access to the private data in the particular physical address interval of the physical memory. The method and the apparatus of the present application can enhance security of private data in a physical memory.

Abstract: An apparatus and method are provided for transferring data between address ranges in memory. The apparatus comprises a data transfer controller, that is responsive to a data transfer request received by the apparatus from a processing element, to perform a transfer operation to transfer data from at least one source address range in memory to at least one destination address range in the memory. A redirect controller is then arranged, whilst the transfer operation is being performed, to intercept an access request that specifies a target address within a target address range, and to perform a memory redirection operation so as to cause the access request to be processed without awaiting completion of the transfer operation.

Abstract: A synchronization of data is performed via remote copy operations from a primary storage controller to a secondary storage controller, wherein input/output (I/O) requests are received at the primary storage controller from a host both via a bus interface and a network interface while the remote copy operations are in progress. A first data structure stores identification of tracks written via the network interface that are to be copied from the primary storage controller to the secondary storage controller for the synchronization of data. A second data structure stores identification of tracks written via the bus interface that are to be copied from the primary storage controller to the secondary storage controller for the synchronization of data.

Abstract: Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.

Abstract: Embodiments of the present invention provide an approach for memory protection at a level of granularity above a “page” level (e.g., enhancing the protection provided by a memory key-based system). The approach further provides such a level of protection at a process or task level by associating the physical page key with a virtual key that corresponds to a particular process/task. When access to the data is requested for a particular process or task, it is determined if a protection bit for the data is set, and if the physical page keys and/or virtual keys submitted pursuant to the request match that previously stored for the data and process/task. If so, access to the data is allowed for the particular process/task.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include flash memory to store data and may support a plurality of device streams. A SSD controller may manage reading and writing data to the flash memory, and may store a submission queue and a chunk-to-stream mapper. A flash translation layer may include a receiver to receive a write command, an LBA mapper to map an LBA to a chunk identifier (ID), stream selection logic to select a stream ID based on the chunk ID, a stream ID adder to add the stream ID to the write command, a queuer to place the chunk ID in the submission queue, and background logic to update the chunk-to-stream mapper after the chunk ID is removed from the submission queue.

Abstract: A technique for operating a data processing system includes determining, by an arbiter of a processing unit of the data processing system, whether an over-commit has occurred. In response to determining that the over-commit has occurred, the arbiter selects a broadcast command to be dropped based on a number of hops traversed through the data processing system by the broadcast command.

Abstract: Systems and methods for flexible management of resources in a Non-Volatile Memory Express (NVMe) virtualization environment are disclosed. In NVMe virtualization, the host device operates in the virtual world and the memory device operates in the physical world. In order for the memory device to perform a host access request (which includes the virtual identification), the memory device transforms the virtual identification into a physical identification. Likewise, prior to the memory device sending a memory device access request to the host device, the memory device transforms the physical identification into the virtual identification. There may be multiple physical resources, such as submission queues/completion queues and interrupt vectors. Rather than having separate translation tables for the queues and the interrupt vectors, a single virtual translation table is used to perform the translation from the virtual identification to the queues and the interrupt vectors.

Abstract: Technologies for memory management of a neural network include a compute device to read a memory of the compute device to access connectivity data associated with a neuron of the neural network, determine a memory address at which weights corresponding with the one or more network connections are stored, and access the corresponding weights from a memory location corresponding with the memory address. The connectivity data is indicative of one or more network connections from the neuron.

Abstract: A storage device includes at least one nonvolatile memory device; and a memory controller configured to control the nonvolatile memory device, wherein the memory controller includes, at least one processor configured to control an overall operation of the memory controller; a buffer memory configured to store input/output data according to a control of the processor when an input/output request from an external device occurs; an error correction circuit configured to detect and correct an error of the input/output data; a garbage collector configured to selectively generate a first global garbage collection command in response to the input/output request and configured to perform a global garbage collection according to a second global garbage collection command received from the external device; and a storage interface configured to transmit the first global garbage collection command to another storage device.

Abstract: A method is provided for providing access to a data block in a device of a processing system. The device is connected to a processor of the processing system via an extension bus, and the processing system includes a memory connected to the processor via a memory bus, an operating system and hardware and/or firmware components for controlling access to the device. The method includes adding by the operating system for the data block a first entry in a page table of the processing system. The added entry represents the data block. A memory management unit (MMU) of the processing system may receive a request of the data block. Upon receiving the request, the MMU may instruct one of the hardware or firmware components to provide access to the data block using the added entry.

Abstract: When writing data to memory via a write buffer including a write cache containing a plurality of lines for storing data to be written to memory and an address-translation cache that stores a list of virtual address to physical address translations, a record of a set of lines of the write cache that are available to be evicted to the memory is maintained, and the evictable lines in the record of evictable lines are processed by requesting from the address-translation cache a respective physical address for each virtual address associated with an evictable line. The address-translation cache returns a hit or a miss status to the write buffer for each evictable line that is checked, and the write buffer writes out to memory at least one of the evictable lines for which a hit status was returned.

Abstract: Disclosed herein are techniques for monitoring the performance of a storage-class memory (SCM). In some embodiments, a performance monitoring circuit at an interface between the SCM and a memory controller of the SCM receives transaction commands from the memory controller to the SCM, measures statistics associated with the transaction commands, and determines a utilization rate of the SCM based on the statistics. Based on the determined utilization rate of the SCM, future transaction requests can be optimized to improve the utilization rate of the SCM.

Abstract: A set of logical containers are maintained in a cache, each logical container corresponding to a portion of a main snapshot catalog. First metadata of a first snapshot created by a first snapshot appliance is examined. Based on the first metadata examination, the first snapshot is cataloged into a first logical container. Second metadata of a second snapshot created by a second snapshot appliance is examined. Based on the second metadata examination, the second snapshot is cataloged into a second logical container, separate from the first logical container. A request is received to perform an operation involving one of the first or second snapshots. The request is matched to one of the first or second logical containers. The one of the first or second logical containers is searched to retrieve a snapshot responsive to the request without searching another of the first or second logical containers.

Abstract: A method of responding to requests to read data from a computerized data storage system is disclosed. The method includes (a) receiving a request to access a set of data stored in an extent of persistent storage of the computerized data storage system, (b) obtaining, from mapping metadata provided for locating the requested extent, a hash digest of the set of data, the hash digest identifying contents of the set of data, (c) indexing into a content-based cache within memory of the computerized data storage system with a key based on the hash digest to locate a cached copy of the set of data within the memory, and (d) returning the cached copy of the set of data from the memory without accessing the extent of data from persistent storage. An apparatus, system, and computer program product for performing a similar method are also provided.

Abstract: Rules are stored for dynamically managing virtual machine backups in a computing environment. Each rule includes a triggering condition and an action to be performed when the triggering condition is satisfied. A selection of at least one rule to apply to the environment is received. The environment is polled to detect changes. The selected at least one rule is evaluated against a detected change. Based on the evaluation, a determination is made that a triggering condition has been satisfied. An action specified in the at least one rule is performed where the action includes one of commissioning a new virtual backup proxy or decommissioning an existing virtual backup proxy.

Abstract: A computer system assembly has a computer system and an external management device, as well as use of a storage unit in a computer system. Included in the computer system, is an energy supply device; as well as a management unit, which controls and/or manages system parameters based upon system parameter data; and, at least one separate interface for connecting an external management device (smartphone, tablet PC or a notebook, for example). The computer system also has at least one storage unit, which is connected to a management unit for the internal exchange of system parameter data. The at least one storage unit is connected to the at least one separate interface for the external exchange of system parameter data and is operable externally by the separate interface(s) independent from the energy supply device.

Abstract: Methods and apparatus for transmit buffers for network devices. One apparatus includes a packing unit, a buffer manager and a plurality of aggregated port buffers, each coupled to receive output from the packing unit. The packing unit is configured to receive packet data as input segments of a first size; generate storage units of a second size; and write each storage unit to a particular aggregated port buffer identified by the buffer manager. The buffer manager is configured to: select a particular aggregated port buffer for each storage unit, and send information to the buffer manager about the selected particular aggregated port buffer; monitor availability of storage space in the aggregated port buffers; control reception of input segments based on storage space availability; and manage transmission of the storage units from the aggregated port buffers to one or more external destinations as output segments of a third size.