Abstract: In an embodiment, an apparatus includes a cache memory and a control circuit. The control circuit may be configured to pre-fetch and store a first quantity of instruction data in response to a determination that a first pre-fetch operation request is received after a reset and prior to a first end condition. The first end condition may depend on an amount of unused storage in the cache memory. The control circuit may be further configured to pre-fetch and store a second quantity of instruction data in response to a determination that a second pre-fetch operation request is received after the first end condition. The second quantity may be less than the first quantity.

Abstract: A mechanism is described for facilitating smart optimization of unused graphics buffer memory in computing environments. A method of embodiments, as described herein, includes detecting a software application at a computing device, where the software application to place a request for a task capable of being executed by a processor of the computing device. The method may further include allocating a composition of buffers and facilitate allocation of physical memory to the buffers to be used to perform the task, where a first portion of the physical memory and a second portion of the physical memory are allocated to first one or more of the buffers and second one or more of the buffers, respectively.

Abstract: Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory where the atomic queue is allocated.

Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic write-only mode ignoring conflicts to certain read-sets of a transaction during transactional execution. Write-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.

Abstract: Configurable operating mode memory devices are disclosed. In at least one embodiment, a memory device is configurable into one or more operating modes. An array of memory cells can be allocated into one or more partitions where each partition is associated only with a particular mode of operation. In at least one other embodiment, a memory device is configured to store user data in a portion of a memory array and to store data corresponding to a logical function associated with a different operating mode of the memory device in a different portion of the memory array.

Abstract: A non-volatile storage device of the present disclosure includes non-volatile memory configured to have a plurality of areas for storing data, and a memory controller configured to write the data to the non-volatile memory and to read the data from the non-volatile memory. The memory controller includes a memory interface (I/F) connected to the non-volatile memory, a threshold calculator calculating a threshold for the number of error bits of the data based on a storage condition in the case of storing the data in the non-volatile memory without power, and a refresh controller determining whether refresh processing of the data is necessary, based on the threshold and the number of error bits of the data, and executing the refresh processing of the data if the refresh processing of the data is necessary.

Abstract: An improved technique for managing data storage includes relocating allocated blocks within a range of a physical address space of a file system to free the allocated blocks. The range has a length equal to a length of one or more full stripes of a RAID group that stores content of the file system. In response to receiving data to be written to the file system, the file system arranges the data in the range of contiguous blocks and performs one or more full-stripe writes to write the data to the RAID group.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a load/store superslice, where the load/store superslice includes a set predict array, a first load/store slice, and a second load/store slice. Operation of such a multi-slice processor includes: receiving a two-target load instruction directed to the first load/store slice and a store instruction directed to the second load/store slice; determining a first subset of ports of the set predict array as inputs for an effective address for the two-target load instruction; determining a second subset of ports of the set predict array as inputs for an effective address for the store instruction; and generating, in dependence upon logic corresponding to the set predict array that is less than logic implementing an entire load/store slice, output for performing the two-target load instruction in parallel with generating output for performing the store instruction.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a load/store superslice, where the load/store superslice includes a set predict array, a first load/store slice, and a second load/store slice. Operation of such a multi-slice processor includes: receiving a two-target load instruction directed to the first load/store slice and a store instruction directed to the second load/store slice; determining a first subset of ports of the set predict array as inputs for an effective address for the two-target load instruction; determining a second subset of ports of the set predict array as inputs for an effective address for the store instruction; and generating, in dependence upon logic corresponding to the set predict array that is less than logic implementing an entire load/store slice, output for performing the two-target load instruction in parallel with generating output for performing the store instruction.

Abstract: A method, medium, and system to receive a request to add a resource to a cache, the resource including a data object and a context item key associated with the resource and uniquely identifying a context of use referenced by the context item key; determine whether the resource is stored in the cache; store, in response to the determination that the resource is not stored in the cache, the resource in the cache; and add the context item key of the resource stored in the cache to a record of reference list of resources.

Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic read-only mode ignoring conflicts to certain write-sets of a transaction during transactional execution. Read-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.

Abstract: A method is provided for cache coherence being based on a hybrid approach relying on hardware-and software-implemented functionalities. In case a processor core is requested to perform a write operation on a memory line missed in the local cache of said core, a hardware-implemented coherence directory ensures that said processor core becomes assigned exclusive write permissions to indicate that the memory line in said local cache is up-to-date after said write. In case the processor core is requested to perform a read operation on a memory line missed in the local cache of said processor core, the coherence directory updates the coherence directory to indicate that none of the processor cores of the system has exclusive write permission on the memory line and relies on software executed on said processor core to ensure that the cached memory line is up-to-date before performing the read operation.

Abstract: A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource.

Abstract: According to one embodiment, a magnetic memory device includes a first memory unit including a first memory array and a first drive unit, a second memory unit including a second memory array and a second drive unit, and a controller. The first memory array includes a first magnetic shift register unit. The second memory array includes a second magnetic shift register unit. The controller subdivides input data into a plurality of one-dimensional bit input arrays. The one-dimensional bit input arrays include a first array and a second array. The controller stores the first array in the first magnetic shift register unit on a last in, first out basis, and stores the second array in the second magnetic shift register unit on a last in, first out basis.

Abstract: A backup storage system and methods implemented by the backup storage system are disclosed. The backup software performs a plurality of backup operations to backup one or more data objects according to a backup schedule. The backup operations may be alternated across a plurality of backup storage devices, and each of the backup operations may operate to store a respective backup data set on one of the backup storage devices. In performing the plurality of backup operations, the backup storage system may create the backup data sets such that each respective backup storage device can be used independently of the other backup storage device(s) to perform a complete recovery of the one or more data objects to any point in time that corresponds to any respective backup data set stored on the respective backup storage device.

Abstract: During a startup process of a host, a request is sent to a DSD to identify storage media of the DSD. Identification information is received from the DSD before executing a driver on the host for interfacing with the DSD. The identification information identifies a first storage media of the DSD in response to the request. A second storage media is later identified using the driver.

Abstract: Embodiments of the present invention provide an approach for memory protection at a level of granularity above a “page” level (e.g., enhancing the protection provided by a memory key-based system). The approach further provides such a level of protection at a process or task level by associating the physical page key with a virtual key that corresponds to a particular process/task. When access to the data is requested for a particular process or task, it is determined if a protection bit for the data is set, and if the physical page keys and/or virtual keys submitted pursuant to the request match that previously stored for the data and process/task. If so, access to the data is allowed for the particular process/task.

Abstract: Embodiments of the approaches disclosed herein include a subsystem that includes an access tracking mechanism configured to monitor access operations directed to a first memory and a second memory. The access tracking mechanism detects an access operation generated by a processor for accessing a first memory page residing on the second memory. The access tracking mechanism further determines that the first memory page is included in a first subset of memory pages residing on the second memory. The access tracking mechanism further locates, within a reference vector, a reference bit that corresponds to the first memory page, and sets the reference bit. One advantage of the present invention is that memory pages in a hybrid system migrate as needed to increase overall memory performance.

Abstract: The disclosure relates to filtering snoops in coherent multiprocessor systems. For example, in response to a request to update a target memory location at a Level-2 (L2) cache shared among multiple local processing units each having a Level-1 (L1) cache, a lookup based on the target memory location may be performed in a snoop filter that tracks entries in the L1 caches. If the lookup misses the snoop filter and the snoop filter lacks space to store a new entry, a victim entry to evict from the snoop filter may be selected and a request to invalidate every cache line that maps to the victim entry may be sent to at least one of the processing units with one or more cache lines that map to the victim entry. The victim entry may then be replaced in the snoop filter with the new entry corresponding to the target memory location.

Abstract: An information processing device includes a processor. The processor is configured to allocate a plurality of allocation unit areas to a virtual volume from a first storage device and a second storage device. The processor is configured to generate evaluation information related to access for each of a plurality of divided areas into which each of the plurality of allocation unit areas is divided. The processor is configured to determine based on the generated evaluation information, when allocation to the virtual volume is changed from a first allocation unit area of the first storage device to a second allocation unit area of the second storage device, a first data transfer order of transferring data in divided area units from the first allocation unit area to the second allocation unit area. The processor is configured to transfer the data in accordance with the first data transfer order.