Patents Examined by Edward Wang
  • Patent number: 9811422
    Abstract: Head start population of an image backup. In one example embodiment, a method for head start population of an image backup may include tracking blocks that are modified in a source storage between a first point in time and a second point in time, head start copying a first portion of the modified blocks into the image backup prior to the second point in time, activating a snapshot on the source storage at the second point in time where the snapshot represents a state of the source storage at the second point in time, and copying, subsequent to the second point in time, from the snapshot and into the image backup, a second portion of the modified blocks that were not yet copied into the image backup by the second point in time.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: November 7, 2017
    Assignee: STORAGECRAFT TECHNOLOGY CORPORATION
    Inventor: Nathan S. Bushman
  • Patent number: 9798673
    Abstract: Techniques are disclosed relating to storing translations in memory that are usable to access data on a recording medium. In one embodiment, a request is sent for a memory allocation within a non-pageable portion of a memory in a computer system. Responsive to the request, allocated memory is received. Translations usable to map logical addresses to physical addresses within a storage device are stored within the allocated memory. In some embodiments, the translations are usable to access an area within the storage device used to store pages evicted from the memory. In one embodiment, a size of the memory allocation is determined based on a size of the area. In another embodiment, a size of the memory allocation is determined based on a size of a partition including the area. In some embodiments, the storage device is a solid-state storage array.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 24, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: James G. Peterson, Igor Sharovar, David Atkisson
  • Patent number: 9778862
    Abstract: A data storing method for storing data in a rewritable non-volatile memory module is provided. The method includes temporarily storing first data into a buffer memory; and starting a flush operation to write the first data from the buffer memory into a first physical programming unit. The method further includes determining whether the first physical programming unit is a lower physical programming unit; and if yes, writing second data into a second physical programming unit, wherein the second physical programming unit belongs to an upper physical programming unit, and the second physical programming unit and the first physical programming unit are formed by the same memory cells disposed on the same word line. Accordingly, the method can effectively prevent the data written during the flush operation from losing due to the programming fail occurred on other physical programming units.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: October 3, 2017
    Assignee: PHILSON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 9740569
    Abstract: Head start population of an image backup. In one example embodiment, a method for head start population of an image backup may include tracking blocks that are modified in a source storage between a first point in time and a second point in time, head start copying a first portion of the modified blocks into the image backup prior to the second point in time and ceasing the tracking of the first portion of the modified blocks as being modified, activating a snapshot on the source storage at the second point in time where the snapshot represents a state of the source storage at the second point in time, and copying, subsequent to the second point in time, from the snapshot and into the image backup, a second portion of the modified blocks that were not yet copied into the image backup by the second point in time.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: August 22, 2017
    Assignee: STORAGECRAFT TECHNOLOGY CORPORATION
    Inventor: Nathan S. Bushman
  • Patent number: 9727335
    Abstract: Embodiments of the present invention provide systems and methods for clearing specified blocks of main storage. In one embodiment, an EADM start subchannel is executed. The instructions of the execution of the EADM start subchannel may include a SAP receiving an ADM request block, which specifies a main-storage-clearing operation command. The address and size of a block of main memory to be cleared by the SAP is specified in an MSB designated by the ADM request block.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Incorporated
    Inventors: Anthony F. Coneski, Beth A. Glendening, Dan F. Greiner, Peter G. Sutton, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 9696919
    Abstract: A technique for managing file systems that support block sharing places a source/copy attribute in each block pointer. The source/copy attribute identifies the respective block pointer as either a source-block pointer or a copy-block pointer. A reference count on each data block maintains a count of the number of source-block pointers pointing to the data block but excludes the number of copy-block pointers pointing to the data block. Block pointers are arranged in block pointer sets (BPSs), and sharing relationships are formed among BPSs and copies of BPSs. The sharing relationships generally keep most block sharing information at the BPS level, with reference counts on data blocks tracking only the number of source-block pointers, which is typically small, often being equal to one.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: July 4, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Vamsi Vankamamidi, David W. Harvey
  • Patent number: 9671960
    Abstract: A rate matching technique may be configured to adjust a rate of cleaning of one or more selected segments of the storage array to accommodate a variable rate of incoming workload processed by a storage input/output (I/O) stack executing on one or more nodes of a cluster. An extent store layer of the storage I/O stack may clean a segment in accordance with segment cleaning which, illustratively, may be embodied as a segment cleaning process. The rate matching technique may be implemented as a feedback control mechanism configured to adjust the segment cleaning process based on the incoming workload. Components of the feedback control mechanism may include one or more weight schedulers and various accounting data structures, e.g., counters, configured to track the progress of segment cleaning and free space usage. The counters may also be used to balance the rates of segment cleaning and incoming I/O workload, which may change depending upon an incoming I/O rate.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: June 6, 2017
    Assignee: NetApp, Inc.
    Inventors: Dhaval Patel, Manish Swaminathan, Edward D. McClanahan, John Muth
  • Patent number: 9672151
    Abstract: A storage system comprises a shared storage environment that includes a storage array having at least one storage volume shared between first and second host devices. The storage system further comprises a server associated with the storage array, at least first and second clients associated with the respective first and second host devices, and a first block cache arranged between the first client and the storage array. The server is configured to coordinate operations of the first and second clients relating to the storage volume shared between the first and second host devices in a manner that ensures coherency of data stored in the first block cache. The server may comprise a storage block mapping protocol (SBMP) server and the first and second clients may comprise respective SBMP clients. The block cache is illustratively implemented using a VFCache or other type of server flash cache.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: June 6, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Gang Ma, Sorin Faibish, Percy Tzelnic, James M. Pedone, Jr.
  • Patent number: 9652252
    Abstract: Circuits and methods for power dependent selection of boot images are disclosed. In an example implementation, an apparatus includes a memory circuit and a processor disposed on an integrated circuit die. The processor is configured to retrieve and execute instructions from the memory circuit. The apparatus also includes a power management circuit configured to determine a value indicative of an amount of power available to power the IC die. A boot loader circuit is coupled to the power management circuit and is configured to select one of a plurality of boot images based on the determined value indicative of the amount of power available. The boot loader circuit loads a set of instructions included in the selected one of the boot images into the memory circuit and enables the processor to execute the set of instructions.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: May 16, 2017
    Assignee: XILINX, INC.
    Inventors: Yatharth K. Kochar, Ramakrishna G. Poolla, Krishna C. Patakamuri, Madhubala Sharma
  • Patent number: 9639430
    Abstract: Machines, systems and methods for performing intermediate data backups, the method comprising monitoring data updates to one or more data blocks in at least a target data storage medium, wherein the target data storage medium is subject to an incremental data backup routine at prescheduled time intervals; in response to determining that said at least one or more data blocks is updated prior to a prescheduled time interval for the incremental data backup routine, performing one or more intermediate data backups to store data from the updated data blocks to at least one backup data storage medium; and in response to determining that said at least one or more data blocks is updated prior to the prescheduled time interval for the incremental data backup routine but after the last of the intermediate data backups, copying data on one or more updated data blocks after the last of the intermediate data backups to the backup data storage medium.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: May 2, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ofer Peretz, Michael Sternberg, Asaf Yeger
  • Patent number: 9632791
    Abstract: Techniques are disclosed relating to a cache for patterns of instructions. In some embodiments, an apparatus includes an instruction cache and is configured to detect a pattern of execution of instructions by an instruction processing pipeline. The pattern of execution may involve execution of only instructions in a particular group of instructions. The instructions may include multiple backward control transfers and/or a control transfer instruction that is taken in one iteration of the pattern and not taken in another iteration of the pattern. The apparatus may be configured to store the instructions in the instruction cache and fetch and execute the instructions from the instruction cache. The apparatus may include a branch predictor dedicated to predicting the direction of control transfer instructions for the instruction cache. Various embodiments may reduce power consumption associated with instruction processing.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: April 25, 2017
    Assignee: Apple Inc.
    Inventors: Muawya M. Al-Otoom, Ian D. Kountanis, Ronald P. Hall, Michael L. Karm
  • Patent number: 9582198
    Abstract: Embodiments of the disclosure provide techniques for creating a compressed mapping structure in a system of resources. For example, a distributed resources system may use delta encoding to store, in memory, numerous entries of dense data structures in the system. In a compressed block of such entries, the distributed resources system encodes the key of each entry as the delta from the key of the previous entry. The content of each entry is encoded similarly. The distributed resources system suppresses the leading zero bits of each resulting field.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: February 28, 2017
    Assignee: VMware, Inc.
    Inventor: William Earl
  • Patent number: 9569367
    Abstract: Exemplary methods for improving cache utilization include in response to receiving a request to store data, storing the data in one of a plurality of cache slots of a cache. In one embodiment, the methods further include after storing the data, setting a status of the cache slot as write pending to indicate that the cache slot contains data which needs to be written to a corresponding destination storage device. The methods include determining an eviction type of the cached data based on whether the destination storage device is a local storage device or a remote storage device. In one embodiment, after copying data from the cache slot to the corresponding destination storage device, marking the cache slot with the determined eviction type. In response to receiving another request to store data, evicting at least one of the cache slots based on the eviction type.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: February 14, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Ian Wigmore, Marik Marshak, Arieh Don, Alexandr Veprinsky
  • Patent number: 9542336
    Abstract: A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventors: Marc Torrant, David Puffer, Blaise Fanning, Bryan White, Joydeep Ray, Neil Schaper, Todd Witter, Altug Koker, Aditya Sreenivas
  • Patent number: 9519615
    Abstract: A system includes a collection of central processing units, where each central processing unit is connected to at least one other central processing unit and a root path into at least 10 Tera Bytes of solid state memory resources. Each central processing unit directly accesses solid state memory resources without swapping solid state memory contents into main memory.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: December 13, 2016
    Assignee: EMC Corporation
    Inventors: Frederic Roy Carlson, Jr., Mark Himelstein, Bruce Wilford, Dan Arai, David R. Emberson
  • Patent number: 9501232
    Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic write-only mode ignoring conflicts to certain read-sets of a transaction during transactional execution. Write-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9495108
    Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic write-only mode ignoring conflicts to certain read-sets of a transaction during transactional execution. Write-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: November 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9489144
    Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic read-only mode ignoring conflicts to certain write-sets of a transaction during transactional execution. Read-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: November 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9489142
    Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic read-only mode ignoring conflicts to certain write-sets of a transaction during transactional execution. Read-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: November 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9465733
    Abstract: A storage device includes at least one nonvolatile memory device; and a memory controller configured to control the nonvolatile memory device, wherein the memory controller includes, at least one processor configured to control an overall operation of the memory controller; a buffer memory configured to store input/output data according to a control of the processor when an input/output request from an external device occurs; an error correction circuit configured to detect and correct an error of the input/output data; a garbage collector configured to selectively generate a first global garbage collection command in response to the input/output request and configured to perform a global garbage collection according to a second global garbage collection command received from the external device; and a storage interface configured to transmit the first global garbage collection command to another storage device.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: October 11, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Geol Lee, Wonju Lee