Abstract: Data to be stored is received from an application. A first type of storage, having a first set of storage properties, and a second type of storage, having a second set of storage properties, are selected from based on an access characteristic associated with the data, the first set of storage properties, and the second set of storage properties. The data is stored in the selected type of storage.

Abstract: Embodiments of the invention provide methods and systems for caching data. One method includes receiving, through a user device, a selection of a set of data items, and determining, with an electronic processor, a storage rate, wherein the storage rate includes an integer (N). The method also include retrieving the set of data items and storing every Nth data item included in the set of data items to a non-transitory memory cache while discarding intervening data items.

Abstract: A virtual storage network may be implemented and exposed as a single virtual namespace, using physical disk storage distributed across multiple computing devices. In various embodiments, each computing device contributing physical disk storage to the virtual storage network may include one or more virtual block devices configured to provide a local interface to the virtual storage network, an application programming interface (API) or other software components to translate the local data access requests into tuple-space operations compatible with the tuple-space data model, and/or a tuple-space storage engine configured to provide access to the data tuple-space of the distributed virtual storage network.

Abstract: Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.

Abstract: Embodiments of the present invention provide an approach for memory protection at a level of granularity above a “page” level (e.g., enhancing the protection provided by a memory key-based system). The approach further provides such a level of protection at a process or task level by associating the physical page key with a virtual key that corresponds to a particular process/task. When access to the data is requested for a particular process or task, it is determined if a protection bit for the data is set, and if the physical page keys and/or virtual keys submitted pursuant to the request match that previously stored for the data and process/task. If so, access to the data is allowed for the particular process/task.

Abstract: A storage manager may be used to schedule requests for a data object stored in data sources of a storage system, such as an object-redundant storage system. The storage manager may iteratively request sets of corresponding blocks of the data object from storage devices of the storage system. As the corresponding blocks are received, the storage manager may store the corresponding blocks in an input buffer. In response to receiving at least a particular number of corresponding blocks, the storage manager may remove the corresponding blocks from the input buffer and decode the corresponding blocks into a block of the data object. In response to free space in the input buffer reaching a threshold amount, the storage manager may request subsequent sets of corresponding blocks of the data object such that at least some corresponding blocks are stored in the input buffer when the threshold amount is reached.

Abstract: A method and information handling system and having a solid state drive (SSD) memory device including NAND flash memory with an SSD controller to execute instructions of an SSD adaptive profiling engine for RAM cache optimization and configured to cache a partial FTL table in RAM including look-up addresses corresponding to LBA segments in the NAND flash memory having access counts reflecting SSD I/O operations. The method and system further configured to determine whether the SSD memory device operation is write intensive (or read intensive) from assessment of stored read access counts and write access counts and further determine whether to load a partial FTL table into RAM cache and use remaining unoccupied RAM space for a data cache to enhance the SSD memory device operations.

Abstract: A rate matching technique may be configured to adjust a rate of cleaning of one or more selected segments of the storage array to accommodate a variable rate of incoming workload processed by a storage input/output (I/O) stack executing on one or more nodes of a cluster. An extent store layer of the storage I/O stack may clean a segment in accordance with segment cleaning which, illustratively, may be embodied as a segment cleaning process. The rate matching technique may be implemented as a feedback control mechanism configured to adjust the segment cleaning process based on the incoming workload. Components of the feedback control mechanism may include one or more weight schedulers and various accounting data structures, e.g., counters, configured to track the progress of segment cleaning and free space usage. The counters may also be used to balance the rates of segment cleaning and incoming I/O workload, which may change depending upon an incoming I/O rate.

Abstract: A computer-implemented method for determining correct devices to use in a mass volume migration environment includes reading an I/O configuration definition for a plurality of devices in the mass volume migration environment and definition of a second set of the plurality of devices, wherein the plurality of devices comprise a first set of the plurality of devices. The method includes executing a migration and annotating the first set and the second set with status identifiers. The method also includes responsive to completing a migration of a device in the first set to the associated corresponding device in the second set, updating the annotation of the migrated device in the first set and the corresponding device in the second set and swapping the migrated device in the first set with the corresponding device in the second set, and continuing the migration of devices of the first set to the second set.

Abstract: A data protecting method, a memory storage apparatus and a memory control circuit unit are provided. The method includes: determining whether a first procedure being executed or about to be executed by the memory storage device is a first type procedure; and if the first procedure being executed or about to be executed by the memory storage device is the first type procedure, temporarily stopping receiving a first data corresponding to a first write command before the first procedure is finished.

Abstract: A technique for managing metadata in a data storage system designates block pointers as either sources or copies, where sources contribute to reference counts of pointed-to structures but copies do not. The technique maintains parent-child relationships between parent BPSs (block pointer sets) and child BPSs, where each BPS includes an array of block pointers. Each child BPS is created as a copy of a parent BPS and has block pointers initially designated as copies. The technique performs a metadata-merge operation to merge the block pointers of the parent BPS into those of a child BPS by promoting attributes of block pointers in the child BPS from copy to source, avoiding any need to perform reference count updates on structures pointed to by promoted block pointers.

Abstract: Systems, devices, and techniques for processor synchronization are described. A described system includes sending, from first processors, release requests to an inclusion monitor, the release requests including an identifier tag; sending, from a second processor, an acquire request to the inclusion monitor circuitry, the acquire request including a weight value and the identifier tag; creating a content addressable memory (CAM) entry based on a receipt of at least one of the release or acquire requests; maintaining a count of the release requests that correspond to the identifier tag by using the entry's arrival counter; causing the first processors to stall if the entry's arrival counter does not satisfy a threshold criterion specified by the entry's weight value or if the acquire request has not been received; storing the acquire request's weight value as the entry's weight value; and releasing the first processors if the entry's arrival counter satisfies the criterion.

Abstract: Techniques are disclosed for transitioning a memory page between memories in a virtual memory subsystem. A unified virtual memory (UVM) driver detects a page fault in response to a memory access request associated with a first memory page, where a local page table does not include an entry corresponding to a virtual memory address included in the memory access request. The UVM driver, in response to the page fault, executes a page fault sequence. The page fault sequence includes modifying the ownership state associated with the first memory page to be central-processing-unit-shared. The page fault sequence further includes scheduling the first memory page for migration from a system memory associated with a central processing unit (CPU) to a local memory associated with a parallel processing unit (PPU). One advantage of the disclosed approach is that the PPU accesses memory pages with greater efficiency.

Abstract: Systems, devices, and techniques for processor synchronization are described. A described system includes exclusion monitor circuitry, a content addressable memory (CAM) coupled with the exclusion monitor circuitry, and processors coupled with the exclusion monitor circuitry. The processors can perform synchronization via the exclusion monitor circuitry using an identifier tag. The exclusion monitor circuitry can utilize the CAM to store information for handling one or more named mutual exclusions. The exclusion monitor circuitry and the CAM can be configured to concurrently handle multiple identifier tags that correspond to different mutual exclusions.

Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.

Abstract: Techniques and a system are provided for managing resources used by user-provided programs. The system includes an application programming interface (API) that allows user-provided programs to access memory resources managed by functions provided by the API. The system stores memory-usage records made during memory allocations. Memory-usage records may be used to identify memory resources, analyze memory usage, and provide other features.

Abstract: Techniques and a system are provided for managing resources used by user-provided programs. The system includes an application programming interface (API) that allows user-provided programs to access memory resources managed by functions provided by the API. The system stores memory-usage records made during memory allocations. Memory-usage records may be used to identify memory resources, analyze memory usage, and provide other features.

Abstract: A cache module leverages storage metadata to cache data of a backing store on a non-volatile storage device. The cache module maintains access metadata pertaining to access characteristics of logical identifiers in the logical address space, including access characteristics of un-cached logical identifiers (e.g., logical identifiers associated with data that is not stored on the non-volatile storage device). The access metadata may be separate and/or distinct from the storage metadata. The cache module determines whether to admit data into the cache and/or evict data from the cache using the access metadata. A storage module may provide eviction candidates to the cache module. The cache module may select candidates for eviction. The storage module may leverage the eviction candidates to improve the performance of storage recovery and/or grooming operations.

Abstract: A storage system connectable to a host includes a plurality of interface units, a plurality of semiconductor memory modules, each being detachably coupled with one of the interface units, and a controller configured to maintain an address conversion table indicating mappings between logical addresses and physical addresses of memory locations in the semiconductor memory modules. When the controller determines that a first semiconductor memory module needs to be detached, the controller converts physical addresses of the first semiconductor memory module into corresponding logical addresses using the address conversion table and copies valid data stored in the corresponding logical addresses to another semiconductor memory module and update the address conversion table to indicate new mappings for the corresponding logical addresses of the valid data.

Abstract: A memory device includes a nonvolatile memory unit and a memory controller. The memory controller is configured to generate a plurality of commands in accordance with requests received from a host and store the commands in a buffer, set a priority level to each of the commands based on contents thereof, and transfer the commands having a first priority level from the buffer to the nonvolatile memory unit during a first time period, and the commands having a second priority level lower than the first priority level from the buffer to the nonvolatile memory unit during a second time period. The first time period and the second time period are fixed recurring time periods, and the second time period begins after expiration of the first time period.