Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells and, more particularly, a temperature update for a memory device are described. A memory array may be operated according to a timing cycle that includes a first interval for performing a first type of operation and a second interval for performing a second type of operation, where a duration of the first interval is greater than a duration of the second type of interval. A temperature related to a temperature of at least a portion of the memory array may be sampled during an interval of the second type, and the memory array may be reconfigured based at least in part on a sampled temperature. The first type of operation may then be performed on a reconfigured memory array during an interval of the first type.

Abstract: A storage system comprises a shared storage environment that includes a storage array having at least one storage volume shared between first and second host devices. The storage system further comprises a server associated with the storage array, at least first and second clients associated with the respective first and second host devices, and a first block cache arranged between the first client and the storage array. The server is configured to coordinate operations of the first and second clients relating to the storage volume shared between the first and second host devices in a manner that ensures coherency of data stored in the first block cache. The server may comprise a storage block mapping protocol (SBMP) server and the first and second clients may comprise respective SBMP clients. The block cache is illustratively implemented using a VFCache or other type of server flash cache.

Abstract: A method and system for a DRAM having a first bank that includes a first sub-array (SA) and a second SA. The first SA includes a first storage unit coupled to a first row-buffer in a first sub-channel (FSC) and a second storage unit in a second sub-channel (SSC). The second SA includes a third storage unit and a fourth storage unit coupled to a second row-buffer. The first SA is associated with a first row address (RA) and the FSC is associated with a first column address (CA) stored in the FSC. The second SA is associated with a second RA and the SSC is associated with a second CA stored in the SSC. The first and second CAs are used to select portions of data from the first and second row-buffers, respectively, for output to a data bus.

Abstract: A technique for operating a data processing system includes transitioning, by a cache, to a highest point of coherency (HPC) for a cache line in a required state without receiving data for one or more segments of the cache line that are needed. The cache issues a command to a lowest point of coherency (LPC) that requests data for the one or more segments of the cache line that were not received and are needed. The cache receives the data for the one or more segments of the cache line from the LPC that were not previously received and were needed.

Abstract: A system and method relates to detecting a hardware event, determining a first virtual memory address associated with the hardware event, wherein the first virtual memory address is associated with a first processing thread, identifying, using the first virtual memory address, an entry of a logical address table, the entry comprising a file descriptor and a file offset associated with a file, identifying a memory address table associated with the file descriptor, translating, using the memory address table, the file offset into a second virtual memory address associated with a second processing thread, and transmitting, to the second processing thread, a notification comprising the second virtual memory address.

Abstract: A storage system connectable to a host includes a plurality of interface units, a plurality of semiconductor memory modules, each being detachably coupled with one of the interface units, and a controller configured to maintain an address conversion table indicating mappings between logical addresses and physical addresses of memory locations in the semiconductor memory modules. When the controller determines that a first semiconductor memory module needs to be detached, the controller converts physical addresses of the first semiconductor memory module into corresponding logical addresses using the address conversion table and copies valid data stored in the corresponding logical addresses to another semiconductor memory module and update the address conversion table to indicate new mappings for the corresponding logical addresses of the valid data.

Abstract: Provided are a computer program product, system, and method for determining space to release in a target volume to which tracks from a source volume are mirrored. A copy of a source volume table for the source volume providing a state of the tracks in the source volume for a consistency group is received. Tracks received from the source volume are written to the target volume to form the consistency group of tracks in the source volume at the target volume. A determination is made of tracks available to release from the copy of the source volume table and space allocated to the determined tracks is replaced. A point-in-time copy is created of the target volume for the consistency group. Complete is returned to forming the consistency group in response to releasing the space and creating the point-in-time copy.

Abstract: A system includes a plurality of processors, each being coupled to each of remaining processors via a cluster of processor interconnects. The cluster of processor interconnects form a data distribution network. The system further includes a plurality of roots coupled to the processors, each root corresponding to one of the processors. Each root comprises a memory controller, one or more branches coupled to the memory controller, and a plurality of memory leaves coupled to the branches, each memory leaf having one or more solid state memory devices. Each of the branches is associated with one or more of the memory leaves and provides access to the associated memory leaves. Each of the processors can access any one of the memory leaves via a corresponding branch of any one of the roots over the data distribution network.

Abstract: A technique for storing data selectively tags write requests received by a data storage system based on whether each write request is directed to a file having a file type on an exclusion list, thereby producing a set of tagged write requests directed to a file type on the exclusion list and a set of untagged write requests directed to a file type not on the exclusion list. The method further includes persistently storing tagged data specified by the set of tagged write requests without first compressing the tagged data, and persistently storing untagged data specified by the set of untagged write requests after compressing the untagged data.

Abstract: Provided are a computer program product, system, and method for determining tracks to release in a source volume being copied to a target volume. A consistency group is formed of tracks in the source volume to copy to the target volume. A volume table providing information on the tracks allocated to the source volume is copied to a volume table copy in a memory providing a state of the tracks in the source volume as of a consistency group time. A determination is made of tracks in the source volume to release for tracks that are indicated in the volume table copy as available to release excluding tracks in the source volume that are written after the consistency group time. Space allocated to the determined tracks is released.

Abstract: Provided are a computer program product, system, and method for determining tracks to release in a target volume mirroring tracks from a source volume. Tracks received from the source volume are written to the target volume to form a consistency group of tracks in the source volume at the target volume. A determination is made of tracks available to release from a volume table providing a state of the tracks in the target volume and space allocated to the determined tracks is released. A point-in-time copy of the target volume is crated and complete is returned to forming the consistency group in response to releasing the space and creating the point-in-time copy.

Abstract: A split head invalidation system includes a first memory including a ring buffer, a second memory, and a processor in communication with the first memory. The processor includes a consumer processor and a producer processor. The consumer processor is configured to maintain a head and tail pointer, detect a request to copy a memory entry from the ring buffer, and consume the memory entry. Consuming the memory entry includes iteratively testing a value associated with the memory entry in a slot indicated by the head pointer, retrieving the respective memory entry from the slot, and advancing the head pointer to the next slot until reaching a threshold quantity of slots. Additionally, the consumer processor is configured to invalidate each slot from the head pointer to the tail pointer after reaching the threshold quantity.

Abstract: Systems and methods for data storage management technology that use task identifiers to manage tasks and ensure storage modifications occur without unnecessary task duplication. An example method may comprise: generating a task identifier on a first device; transmitting a request comprising the task identifier to create a task on a second device, the task being associated with the task identifier and comprising the allocation of a data storage portion on a shared storage; determining a reply to the task is missing; and in response to determining the reply is missing, detecting whether the task was created on the second device.

Abstract: In one embodiment, a method includes receiving an input/output (I/O) request for data that starts or ends at a location other than a physical sector boundary of the device. The method further includes reading, starting at a first physical sector boundary before a beginning location specified in the I/O request and ending at a second physical sector boundary after an ending location specified in the request.

Abstract: Systems and methods embed a random-access non-volatile memory array in a managed-NAND system to execute the boot code or other time-sensitive applications. By embedding this random-access non-volatile memory in the managed-NAND system, either on the memory controller chip or as a separate chip within the managed-NAND system package, an application may be read with fast initial access time, alleviating the slow access time limitations of NAND Flash technology. Depending on the size of the application, the system may be configured to read the whole application content or only a time-critical portion from this embedded random-access non-volatile memory array.

Abstract: Techniques are provided for managing cached data objects in a mixed workload environment. In an embodiment, a database system receives request to access a target data object. The database system determines whether the request to access the target data object is associated with a first type of workload or a second type of workload. In response to determining that the request is associated with the first type of workload, the target data object replaces a least recently used data object in a cache. In response to determining that the request is associated with the second type of workload, the target data object is cached based on an associated access-level value.

Abstract: A memory system includes: a memory device comprising a plurality of dies each die comprising a plurality of planes, each plane comprising a plurality of blocks, each block comprising a plurality of pages; a controller suitable for inputting a plurality of commands received from a host to the memory device through command queuing, wherein a first memory die among the plurality of memory dies processes the plurality of commands as a burst command, and performs command operations in one or more pages in one or more first memory blocks included in the first memory die, and data corresponding to the command operations are stored in a plurality of latches corresponding to the one or more first memory blocks.

Abstract: A real time memory address translation device is described herein. The address translation device operates to change memory addresses from one address space that is used by system buses to another address space that is used by a main memory of the associated system. The translation device may be placed on the same chip as a corresponding processor core, for example, on a system on chip. The on-chip arrangement of the translation device enables predictable translation times to meet real-time requirement of time-sensitive subsystems.

Abstract: A device is configured to control a programmable integrated circuit having a plurality of first areas each of which has the same shape and a plurality of second areas formed between the plurality of first areas. The device includes: a memory; and a processor configured to: recognize an operation request executed by the programmable integrated circuit, select a third area and a fourth area used for configuring an operational circuit, by which processing pertaining to the operation request, from the plurality of first areas and the plurality of second areas, cause the selected third area and the selected fourth area to function as an operation processing unit to generate the operational circuit, cause the generated operational circuit to execute processing pertaining to the operation request, and after the processing is completed, cause the third area included in the operational circuit to function as a communication path.

Abstract: Systems, devices and methods for the assessment and mitigation of risk associated with the potential loss of data stored by an IHS (Information Handling System). The risk assessment incorporates contextual and behavioral data provided by the IHS where the data describes file operations by the IHS, the physical use of the IHS, system information that describes the platform of the IHS and hardware installed on the IHS and data backup procedures implemented by the IHS. Based on the data associated with an IHS, a scoring algorithm determines a behavioral risk of loss that reflects the use of the IHS and a contextual risk of loss that reflects user input to individual files, thus indicating the time required to recreate a file. The backup procedures implemented by the IHS are then evaluated in light of the determined risk assessment. Backup procedure recommendations that mitigate the identified risks are provided to the IHS.