Abstract: A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where the test controller selects fail data including a fail data bit among internal data output from the multiple regions during the PBT, and outputs the fail data via a data input/output signal line to the outside of the memory device.

Abstract: A memory control component encodes over-capacity data into an error correction code generated for and stored in association with an application data block, inferentially recovering the over-capacity data during application data block read-back by comparing error syndromes generated in detection/correction operations for respective combinations of each possible value of the over-capacity data and the read-back application data block.

Abstract: Provided herein are method and apparatus for channel coding in the fifth Generation (5G) New Radio (NR) system. An embodiment provides an apparatus for a Next Generation NodeB (gNB), including circuitry, which is configured to: generate Downlink Control Information (DCI) payload for a NR-Physical Downlink Control Channel (NR-PDCCH); attach Cyclic Redundancy Check (CRC) to the DCI payload; mask the CRC with an Radio Network Temporary Identifier (RNTI) using a bitwise modulus 2 addition operation, wherein the number of bits for the RNTI is different from the number of bits for the CRC; and perform polar encoding for the DCI payload with the masked CRC.

Abstract: An example system includes a processing resource and a switch board coupled to a system under test (SUT) and the processing resource. The SUT includes a memory device. The switch board can be configured to provide power to the SUT, communicate a first signal from the SUT to the processing resource, and provide a second signal to the SUT that simulates an input to the SUT during operation of the SUT. The processing resource can be configured to receive a function, selected from a library of functions, to execute during a test of the memory device and cause the switch board to provide the second signal during the test of the SUT.

Abstract: Systems, methods, and instrumentalities are described herein that may be used for reduced complexity polar encoding and decoding. There may be a set of encoding nodes to be used for polar encoding. An encoding node may be associated with a bit index and/or a relaxation level. A relaxation attribute may be selected for the encoding node. A relaxation group may be determined based on the relaxation attributes. The relaxation group may include two encoding nodes associated with consecutive bit indexes, an initial relaxation level, and the first relaxation attribute. A final relaxation level may be determined. Relaxation may be performed on the encoding nodes in the relaxation group. For example, an XOR operation between the encoding nodes may be omitted. Relaxation may be performed on the encoding nodes associated with each relaxation level up to the final relaxation level.

Abstract: Apparatuses, systems, and methods for self-test mode abort circuit. Memory devices may enter a self-test mode and perform testing operations on the memory array. During the self-test mode, the memory device may ignore external communications. The memory includes an abort circuit which may terminate the self-test mode if it fails to properly finish. For example, the abort circuit may count an amount of time since the self-test mode began and end the self-test mode if that amount of time meets or exceeds a threshold, which may be based off of the expected amount of time for the testing operations to complete.

Abstract: A replaceable unit includes a communication unit to perform communication with a main body, and a non-volatile memory storing code information indicating whether a configuration of an error detection code is a first configuration or a second configuration. The communication unit stores, in a volatile memory, the code information, executes the communication in accordance with the code information in the volatile memory, and, upon receiving a change command, updates the code information stored in the volatile memory. The first configuration uses an error detection code of a first code length, the second configuration uses an error detection code of a second code length longer than the first code length, and the first configuration is used for the change command in order to change from the first configuration to the second configuration.

Abstract: Disclosed are various approaches for a controller that can generate and use non-stationary polar codes for encoding and decoding information. In one example, a method includes performing, by an encoder of the controller, a linear operation on at least one vector of information to be stored in a memory. The linear operation includes generating a polar encoded representation from the at least one vector of information. The linear operation also includes generating an output using at least one permutation that is based on a statistical characterization analysis of channels of the memory and a channel dependent permutation that is applied to the polar encoded representation. In some aspects, the statistical characterization analysis includes a respective reliability level of each one of the plurality of channels, and the channel dependent permutation includes an ordered permutation that orders the channels according to their respective reliability level.

Abstract: Systems and methods related to memory devices that may perform error check and correct (ECC) functionality. The systems and methods may employ ECC logic that may be shared between two or more banks. The ECC logic may be used to perform memory operations such as read, write, and masked-write operations, and may increase reliability of storage data.

Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.

Abstract: Provided herein are method and apparatus for channel coding in the fifth Generation (5G) New Radio (NR) system. An embodiment provides an apparatus for a Next Generation NodeB (gNB), including circuitry, which is configured to: generate Downlink Control Information (DCI) payload for a NR-Physical Downlink Control Channel (NR-PDCCH); attach Cyclic Redundancy Check (CRC) to the DCI payload; mask the CRC with an Radio Network Temporary Identifier (RNTI) using a bitwise modulus 2 addition operation, wherein the number of bits for the RNTI is different from the number of bits for the CRC; and perform polar encoding for the DCI payload with the masked CRC.

Abstract: Techniques of memory tiering in computing devices are disclosed herein. One example technique includes retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.

Abstract: An example method may include identifying, in a plurality of blocks of data, one or more unallocated blocks, wherein the plurality of blocks further comprises one or more allocated blocks, generating a plurality of checksums, wherein each checksum corresponds to one of the blocks, and the checksums comprise a plurality of first checksums and a plurality of second checksums, wherein each of the first checksums corresponds to one of the unallocated blocks and comprises a predetermined checksum of a block of zeros, and wherein each of the second checksums corresponds to one of the allocated blocks and comprises a checksum of the corresponding one of the allocated blocks, and generating a result checksum in view of the plurality of checksums.

Abstract: Embodiments provide an interleaver for interleaving an LDPC encoded bit sequence, wherein the interleaver includes a segmentation stage configured to segment the LDPC encoded bit sequence into a plurality of chunks including a first chunk and one or more other chunks, a first interleaver stage, configured to interleave the one or more other chunks or a concatenated version thereof, a second interleaver stage, configured to block wise interleave the first chunk and an interleaved bit sequence provided by the first interleaver stage, to obtain an interleaved version of the LDPC encoded bit sequence, wherein the first chunk consists of bits of a first type being, which are error correcting bits or repeat accumulate bits of the LDPC encoded bit sequence, or are represented, in a Tanner graph representation of the LDPC encoded bit sequence, by variable nodes that include non-random connections to at least two error correcting check nodes.

Abstract: Apparatuses, systems, and methods for error correction for selected bit pairs. A memory device may include an error correction code (ECC) circuit which may receive data bits as part of a read or write operation and generate parity bits based on the data bits. The parity bits may be used to locate and correct errors in the data bits. The parity bits may be generated based on a syndrome value. Each of the individual data bits may be associated with a syndrome value. In addition, some selected pairs of data bits may also be associated with a syndrome value. This may allow the ECC circuit to correct errors in individual data bits or in one of the selected pairs of data bits. In some embodiments, the selected pairs may represent adjacent memory cells along a word line.

Abstract: A wireless receiving device comprises a low-density parity check (LDPC) decoding circuit, comprising a circular shifter constructed and arranged to simultaneously process multiple code words of a parity check matrix configured for different wireless communication standards, including performing a cyclic shift operation of the multiple code words to align with one or more requisite check nodes of a decoder and a logic circuit at an output of the circular shifter constructed and arranged for a matrix larger than the parity check matrix and that includes components having excess hardware due to the construction and arrangement for the larger matrix to decode the multiple code words of the smaller parity check matrix for output to the one or more requisite check nodes.

Abstract: In encoding systems and methods, data or information is encoded using one or more encoding methodologies to generate encoded data or information corresponding to the data or information. Similarly, in decoding systems and methods, encoded data or information is decoded using one or more decoding methodologies to generate the data or information corresponding to the encoded data or information. The encoding/decoding systems and methods can include polar encoding/decoding systems and methods operable for encoding data or information to generate polar codes and for decoding polar codes to generate the corresponding data or information. The information or data can be control information and application data for communication over networks. The networks can include wireless and wireline networks, and network segments, links or channels, including mixed wireline and wireless networks.

Abstract: A transmitting node determines data for a first service will be transmitted during a time period when data for a second service will be transmitted. The data for the first service requires lower latency than the data for the second service and the data for the first service includes an original set of data for the first service and at least one repetition of the original set of data for the first service. The transmitting node adjusts resources consumed by the data for the first service based on available transmission resources. During the time period the transmitting node then transmits the data for the first service using the adjusted resources while data for the second service is transmitted during the time period.

Abstract: A test circuit includes a comparator and a comparison control circuit. The comparator is configured to compare a first input signal with a second input signal to generate a comparison result signal. The comparison control circuit is configured to perform at least one of an operation for latching the comparison result signal as reference data and an operation for outputting the comparison result signal as a first output signal. The comparison control circuit is configured to provide expectation data as the first input signal and read data as the second input signal in accordance with the reference data.

Abstract: According to one embodiment, a magnetic disk device includes a disk, a head that writes data to the disk and reads data from the disk, and a controller that corrects a first signal into a first likelihood value by machine learning based on a correct learning signal set with a likelihood other than 1 and an incorrect learning signal set with a likelihood other than 0 and executes error correction processing based on a second likelihood value according to the first signal and the first likelihood value.