Abstract: An example system includes a processing resource and a switch board coupled to a system under test (SUT) and the processing resource. The SUT includes a memory device. The switch board can be configured to provide power to the SUT, communicate a first signal from the SUT to the processing resource, and provide a second signal to the SUT that simulates an input to the SUT during operation of the SUT. The processing resource can be configured to receive a function, selected from a library of functions, to execute during a test of the memory device and cause the switch board to provide the second signal during the test of the SUT.

Abstract: A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.

Abstract: A novel architecture provides many of the advantages of the array and datapath architecture of DRAM products that do not utilize ECC (error correction code) functionality, while simultaneously allowing the flexible deployment of ECC error correction as needed. Aspects of the disclosure enable the minimization of write and read latency typically introduced by the implementation of ECC error correction. Sharing of circuit components between neighboring memory regions is also introduced, which allows for a reduction in circuit area as well as a reduction in loading on speed-critical data bus wiring, which improves overall performance. A very fast single error correct (SEC) and double error detect (DED) read-out for real-time system-level awareness is also provided.

Abstract: Certain aspects of the present disclosure generally relate to techniques for enhanced puncturing and low-density parity-check (LDPC) code structure. A method for wireless communications by a transmitting device is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a base matrix having a first number of variable nodes and a second number of check nodes; puncturing the code word according to a puncturing pattern designed to puncture bits corresponding to at least two of the variable nodes to produce a punctured code word; adding at least one additional parity bit for the at least two punctured variable nodes; and transmitting the punctured code word.

Abstract: A method of transmitting a broadcast signal includes encoding mobile data for FEC (Forward Error Correction); encoding signaling information for signaling the mobile data; allocating the encoded mobile data and signaling data into a transmission frame; and transmitting the broadcast signal including the transmission frame, wherein the transmission frame includes a service signaling table having service type information identifying a type of a service of the mobile data and hidden information indicating whether the service of the mobile data is hidden or not.

Abstract: Provided are a memory controller determining degradation in endurance, a memory system including the memory controller, and a method of operating the memory controller. The memory controller includes: an error correction code (ECC) circuit configured to detect an error from data read from a memory device; and an endurance determination circuit configured to check a first counting value indicating a number of writing operations on the memory device and a second counting value indicating, based on the data read from the memory device, at least one of: a number of first memory cells of the memory device, each of the first memory cells having an error and a number of second memory cells of the memory device in a certain logic state, and configured to perform a first determination operation for determining whether endurance of the memory device has degraded based on a checking result.

Abstract: A transmitting node determines data for a first service will be transmitted during a time period when data for a second service will be transmitted. The data for the first service requires lower latency than the data for the second service and the data for the first service includes an original set of data for the first service and at least one repetition of the original set of data for the first service. The transmitting node adjusts resources consumed by the data for the first service based on available transmission resources. During the time period the transmitting node then transmits the data for the first service using the adjusted resources while data for the second service is transmitted during the time period.

Abstract: Systems and methods related to memory devices that may perform error check and correct (ECC) functionality. The systems and methods may employ ECC logic that may be shared between two or more banks. The ECC logic may be used to perform memory operations such as read, write, and masked-write operations, and may increase reliability of storage data.

Abstract: A method includes receiving a data retrieval request. A plurality of identifiers are determined in accordance with the data retrieval request. Stored integrity information corresponding to the data retrieval request is received. Desired integrity information is generated based on the plurality of identifiers. The stored integrity information is compared with the desired integrity information. When the stored integrity information compares favorably with the desired integrity information, at least a decode threshold number of encoded data slices of a set of encoded data slices of a plurality of sets of encoded data slices are dispersed storage error decoded.

Abstract: Various methods, computer storage media, and systems for implementing hierarchical data integrity verification, in distributed computing systems, are provided. A data manager operates to perform hierarchical data integrity verification operations on message-digests that are associated based on a linear property of a non-cryptographic function, such that a data integrity of source data is verifiable based on the message-digests combined based on an exclusive-or (XOR) operator. The data manager accesses data fragments that are erasure coded fragments and a parity fragment generated from the data fragments, which correspond to source data. The data manager generates and stores the data-fragment message-digests, data-parity message-digests, and parity-fragment message-digests in corresponding data fragment zones and parity fragment zones.

Abstract: Systems and methods for packet re-transmission via a bi-directional wired interface between two devices are provided. A transmitter of a first device transmits one or more first transmit data packets to a second device over the bi-directional wired interface. Concurrently with the transmission of the one or more first transmit data packets, the first device receives, over the bi-directional wired interface, one or more second received data packets from the second device. A packet integrity monitor of the first device monitors whether one or more received data packets of the second received data packets is corrupted at the physical layer of the first device. In response to detecting that one or more received data packets of the second received data packets is corrupted, the first device re-transmits one or more transmit data packets of the first transmit data packets that was previously transmitted over the bi-directional wired interface.

Abstract: Technologies for error recovery in compressed data streams include a compute device configured to compress uncompressed data of an input stream to generate compressed data, perform a compression error check on the compressed data to verify integrity of the compressed data, and determine, as a result of the performed compression error check, whether the compressed data included a compression error. The compute device is further configured to transfer, in response to a determination that the performed compression error check indicated that the compressed data included the compression error, the uncompressed data into a destination buffer, and store an indication with the uncompressed data into the destination buffer, wherein the indication is usable to identify that the uncompressed data has been transferred into the destination buffer. Other embodiments are described herein.

Abstract: A memory system includes a memory device having a plurality of volatile memory modules therein, and a memory controller, which is electrically coupled to the plurality of volatile memory modules. The memory controller is configured to correct an error in a first of the plurality of volatile memory modules in response to generation of an alert signal by the first of the plurality of volatile memory modules, concurrently with an operation to refresh at least a portion of a second of the plurality of volatile memory modules upon the generation of the alert signal.

Abstract: Embodiments use Bayesian techniques to efficiently estimate the bit error rates (BERs) of cables in a computer network at a customizable level of confidence. Specifically, a plurality of probability records are maintained for a given cable in a computer system, where each probability record is associated with a hypothetical BER for the cable, and reflects a probability that the cable has the associated hypothetical BER. At configurable time intervals, the probability records are updated using statistics gathered from a switch port connected to the cable. In order to estimate the BER of the cable at a given confidence level, embodiments determine which probability record is associated with a probability mass that indicates the confidence level. The estimate for the cable BER is the hypothetical BER that is associated with the indicated probability mass. Embodiments store the estimate in memory and utilize the estimate to aid in maintaining the computer system.

Abstract: An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.

Abstract: Enhanced error correction for data stored in storage devices are presented herein. An error correction circuit decodes an encoded data segment retrieved from a storage media. This decode uses a selected error correction scheme having an error correction limit. The error correction circuit tracks a number of bit corrections made to the encoded data segment during decode. A detection circuit sends a redundant version of the encoded data segment to the error correction circuit in response to the number of bit corrections satisfying a threshold limit set below the error correction limit to mitigate undetected errors in decoding the encoded data segment. An output circuit can transfer resultant data decoded by the error correction circuit to other systems, such as a host device.

Abstract: Correction data units for data packets of a data stream are generated. A correction data unit is based on a set of the data packets of the stream. The stream is transmitted over a communication channel. A performance measure to be optimized is selected, which relates to the recovery of lost data packets of the stream. To optimize the performance measure, a plurality of correction data vectors are determined, and a plurality of a plurality of non-recovery probabilities, corresponding to the correction data vectors, are initialized. One or more of the correction data vectors are selected that contribute towards a non-recovery probability of an original data packet. The non-recovery probability associated with the original data packet is then minimized based on the selected one or more correction data vectors. The selected one or more correction data vectors are then used to determine which of the original data packets or data correction units to transmit.

Abstract: A master includes a transmission and receiving unit that transmits and receives signals to and from a slave, and the transmission and receiving unit receives read data read out from the slave, and typically drives the second bit of a preamble transmitted/received subsequent to the read data. The master can notify the slave that communication is or is not interrupted at some midpoint, on the basis of the second bit of the preamble. The present technology can be applied to a bus IF that communicates pursuant to, for example, the specification of I3C.

Abstract: An apparatus for generating encoded data includes processing circuitry configured to encode data using a Mojette transform (MT) based on generating encoded representations of data blocks. Generating the encoded representations of data blocks includes reading data in the form of a data block formatted according to specified settings to comprise rows and columns, creating a set of projections, and outputting the created set of projections to enable storage of the data in the form of the set of projections. The apparatus then transmits the encoded data over a network to another device. Additionally, creating the set of projections includes applying the Mojette transform on the data block, and creating a first number of projections based on mapping each row of the data block to a corresponding projection, wherein the first number of projections carries the same information as a corresponding row.

Abstract: A method for checking the availability and integrity of a data object stored on a plurality of servers and having a number N of data words. For the distributed storage on the servers, the data object is fragmented. Each fragment is transmitted to and stored on one server. To check the availability and integrity of the fragments stored on the servers, the same random number is sent from an auditor unit to the servers. A checksum is created by the servers, in each case modified by application of the random number to the data of the respective fragment, and the checksum is transmitted to the auditor unit. The auditor unit uses the consistency check to determine whether the individual checksums sent by the servers are consistent and, if this is the case, establishes the availability and integrity of the data.