Abstract: Provided is a method for detecting stored data and device, a storage medium and an electronic device. The method includes: the first check information of first data stored in a memory in the current period is determined; the first check information is compared with second check information to obtain a check result, wherein the second check information is check information of second data stored in the memory in a period prior to the current period; and the correctness of storage of the second data is detected according to the check result.

Abstract: A method includes receiving a data retrieval request. A plurality of identifiers are determined in accordance with the data retrieval request. Integrity information is generated based on determining the plurality of identifiers by performing a cyclic redundancy check. Stored integrity information corresponding to the data retrieval request is compared with the integrity information, where the stored integrity information was previously generated by performing the cyclic redundancy check. When the stored integrity information compares unfavorably with the integrity information, corruption associated with the plurality of identifiers is determined.

Abstract: According to one embodiment, there is provided a memory system including a non-volatile memory, and a controller. The controller selects one read method from a plurality of read methods with different time required to perform a read operation on the non-volatile memory and issues a first read command according to the selected one read method to the non-volatile memory.

Abstract: An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.

Abstract: The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.

Abstract: A method performed by a controller of a solid state drive comprising receiving from a host a read request for read data stored in nonvolatile semiconductor storage devices of the solid state drive. The method also comprises identifying a first codeword and a second codeword, the first codeword and the second codeword comprising the read data corresponding to the read request. Responsive to the read request, the method comprises reading a first portion of the read data contained in the first codeword and reading a second portion of the read data contained in the second codeword, assembling the first portion and the second portion as assembled read data, and transferring the assembled read data to the host responsive to the read request. The first and second codewords are adjacently stored, and the assembled read data has a length that is greater than the length of the first and second codewords.

Abstract: Systems, methods, and instrumentalities are described herein that may be used for reduced complexity polar encoding and decoding. There may be a set of encoding nodes to be used for polar encoding. An encoding node may be associated with a bit index and/or a relaxation level. A relaxation attribute may be selected for the encoding node. A relaxation group may be determined based on the relaxation attributes. The relaxation group may include two encoding nodes associated with consecutive bit indexes, an initial relaxation level, and the first relaxation attribute. A final relaxation level may be determined. Relaxation may be performed on the encoding nodes in the relaxation group. For example, an XOR operation between the encoding nodes may be omitted. Relaxation may be performed on the encoding nodes associated with each relaxation level up to the final relaxation level.

Abstract: A memory controller including, in one implementation, a memory interface and a control circuit. The memory interface is configured to receive a punctured codeword read from a non-volatile memory. The control circuit is configured to determine error probability values for a plurality of check nodes associated with a punctured bit included in the punctured codeword. The control circuit is also configured to determine an error probability value for the punctured bit based on the error probability values for the plurality of check nodes associated with the punctured bit and a variable degree associated with the punctured bit. The control circuit is further configured to determine a log likelihood ratio (LLR) value for the punctured bit based on the error probability value for the punctured bit. The control circuit is also configured to decode the punctured codeword using the LLR value for the punctured bit.

Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.

Abstract: A processing device in a memory sub-system identifies a stream of data that is associated with an exclusive-or (XOR) calculator component generating first parity data for data from the stream of data that is stored in a memory sub-system. The processing device further receives one or more characteristics associated with the stream of data, and assigns the stream of data to a buffer memory of the XOR calculator component based on the received one or more characteristics.

Abstract: A memory system may include: one or more memory devices each including a plurality of memory cells for storing data; a memory for storing meta data associated with the stored data; and a memory controller in communication with the memory and the one or more memory devices and for loading the meta data from the memory, and generating first meta page based on the meta data according to a first layout, and storing the first meta page in the memory device.

Abstract: A graphics processing system for operation with a data store, comprising: one or more processing units for processing tasks; a check unit operable to form a signature which is characteristic of an output from processing a task on a processing unit; and a fault detection unit operable to compare signatures formed at the check unit; wherein the graphics processing system is operable to process each task first and second times at the one or more processing units so as to, respectively, generate first and second processed outputs, the graphics processing system being configured to: write out the first processed output to the data store; read back the first processed output from the data store and form at the check unit a first signature which is characteristic of the first processed output as read back from the data store; form at the check unit a second signature which is characteristic of the second processed output; compare the first and second signatures at the fault detection unit; and raise a fault signal i

Abstract: A controller is coupled to a non-volatile memory device and a host. The controller is configured to perform a cyclic redundancy check on map data associated with user data stored in the memory device, generate an encryption code based on a logical address included in the map data, generate encrypted data through a logical operation on the encryption code and the map data, and transmit the encrypted data to the host.

Abstract: A method for selectively inverting a word to be written to a memory is provided. The memory includes memory cells, each memory cell allowing at least two values associated with at least one bit to be stored, the decision as to whether to invert a word being made depending on a number of vulnerable values, which number is determined on the basis of the data bits, of the inversion bit and of uneven check bits.

Abstract: A quantum computing system and methods for performing fault-tolerant quantum computing. A fusion controller sequentially performs a series of fusion measurements on different fusion sites of a plurality of fusion sites to obtain a respective series of classical measurement results. The series of fusion measurements is performed on quantum modes of a logical qubit. For respective fusion measurements of the series of fusion measurements, a basis for performing the respective fusion measurement is selected based on classical measurement results of previous fusion measurements. The series of classical measurement results are in the memory medium.

Abstract: Methods and circuits for storing column redundancy data are provided herein. A circuit may comprise a column redundancy data array, which may store an address and a plurality of match bits. A first portion of bits of the address may reference a range of columns of a memory array and a second portion of bits of the address may reference a division of the memory array in which a column of the range of columns is located. Each of the match bits may indicate whether one of the columns of the range of columns is defective.

Abstract: A transmitter according to the disclosure includes: an encoding unit that generates a code word by performing coding with a low-density parity-check code using a check matrix, the encoding unit being capable of switching the check matrix for use in generating the code word, between a first check matrix with a first code rate and a second check matrix with a second code rate smaller than the first code rate, the first check matrix containing a plurality of cyclic permutation matrices, the encoding unit generating the second check matrix by masking the cyclic permutation matrix at a predetermined position in the first check matrix and adding a row with a column weight equal to or less than a threshold; and a transmission unit that transmits the code word.

Abstract: A method includes encoding data via erasure coding to produce a plurality of data slices. The method further includes determining a plurality of identifiers corresponding to the data. The method further includes generating integrity information based on the plurality of identifiers by performing a cyclic redundancy check. The method further includes storing the plurality of data slices, the plurality of identifiers, and the integrity information in a storage system.

Abstract: The present disclosure provides a polar code coding method, a polar code decoding method, apparatus and device. The polar code coding method includes: obtaining a plurality of CRC check bits; determining interleaved padding positions in a to-be-coded sequence; filling a first predetermined number of CRC check bits of the plurality of CRC check bits into the interleaved padding positions in the to-be-coded sequence in an interleaving manner; and performing polar coding on the to-be-coded sequence that is filled with the predetermined number of CRC check bits in interleaving manner, and transmitting a coded sequence to a receiving end. The first predetermined number is less than or equal to a total number of the plurality of CRC check bits.

Abstract: A method generates a frozen vector associated with a polar code codeword on the basis of a frozen matrix associated with a product code codeword, the frozen matrix being of size Nc×Nr. The method includes replicating a first matrix row of the frozen matrix Nc times to generate an expanded matrix row; replicating a first matrix column of the frozen matrix Nr times to generate an expanded matrix column; generating the frozen vector on the basis of the expanded matrix row and the expanded matrix column. The disclosure further provides a method for generating a frozen matrix associated with a product code codeword on the basis of a frozen vector associated with a polar code codeword, wherein the product code codeword comprises a matrix of size Nc×Nr, and the frozen vector comprises a vector of size N with a plurality of bits.