Abstract: Identification of communication participants may be an important aspect of various communication systems. For example, fifth generation (5G) wireless communication systems may benefit from suitable recipient identification. A method can include obtaining data bits to be communicated to a target device. The method can also include obtaining identification bits corresponding to at least one of sender or receiver of the data bits. The method can further include multiplexing the data bits with the identification bits.

Abstract: In order to enable a seamless configuration modification during operation, a first automation device sends a second automation device a request for parameter modification. The second automation device responds to the request, such that a standby acknowledgement of the request is sent. Immediately with the transmission of the standby acknowledgement in the second automation device, an output process image is frozen, and the modification of the communication parameters for the second automation device is carried out. The first automation device responds, such that after receiving the standby acknowledgement in the first automation device, the communication is immediately stopped and the modification of the communication parameters is carried out for the first automation device. An input process image is frozen.

Abstract: Certain aspects of the present disclosure provide techniques for wireless communication. The techniques include a method wireless communication by a user equipment including receiving a configuration message, wherein the configuration message in part configures the UE to communicate coordinated transmissions with a plurality of transmission reception points using a coordinated transmission mode. The method further includes, receiving one or more physical downlink shared channel transmissions from a plurality of transmission reception points in accordance with the coordinated transmission mode. The method further includes, selecting a HARQ-ACK feedback mode based in part on the coordinated transmission mode. The method further includes, transmitting HARQ-ACK feedback to at least one of the plurality of transmission reception points using the selected HARQ-ACK feedback mode.

Abstract: A method, computer program product, and computer system for storing, by a computing device, a plurality of objects from a buffer to a sector on persistent storage. Protection may be applied to an object of the plurality of objects. An index may be generated to lock the object in the sector. The object of the plurality of objects may be stored from the buffer to the sector on the persistent storage based upon, at least in part, the index, wherein the sector on the persistent storage may include the plurality of objects.

Abstract: The disclosed systems, structures, and methods are directed to encoding and decoding information for transmission across a communication channel. The method includes dividing the information between m parallel polar codes such that each of the m parallel polar codes includes a plurality of information bits, and splitting the information bits in each of the m parallel polar codes into a private part and a public part. The public part includes an information section and a repetition section, wherein the information bits of the public part are arranged in the information section. Bits in the information section of the public part of each of the m parallel polar codes are repeated in the repetition section of the public part of at least a second one of the m parallel polar codes.

Abstract: In order to reduce write tail latency, a storage system generates redundant write requests when performing a storage operation for an object. The storage operation is determined to be effectively complete when a minimum number of write requests have completed. For example, the storage system may generate twelve write requests and also generate four redundant write requests for a total of sixteen write requests. The storage system considers the object successfully stored once twelve of the sixteen writes complete successfully. To generate the redundant writes, the storage system may use replication or erasure coding. For replication, the storage system may issue a redundant write request for each of n chunks being written. For erasure coding, the storage system may use rateless codes which can generate unlimited number of parity chunks or use an n+k+k? erasure code which generates an additional k? encoded chunks, in place of an n+k erasure code.

Abstract: The disclosure provides a method and a device in a User Equipment (UE) and a base station for wireless communication. A first node generates a first bit block, performs channel coding and then transmits a first radio signal. The first bit block comprising all bits in a second bit block and all bits in a third bit block is used for an input of the channel coding, and an output of the channel coding is used for generating the first radio signal. A Cyclic Redundancy Check (CRC) bit block of a fourth bit block is used for generating the third bit block. The fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the bits in the fifth bit block are of fixed values, and the fifth bit block is composed of K bits, the K being a positive integer.

Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.

Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.

Abstract: One embodiment provides a system and method for facilitating error-correction protection in a storage device. In response to a write request, the system organizes a block of data in a two-dimensional (2D) array, forms a plurality of first-dimension sub-blocks by dividing the 2D array along a first dimension, and forms a plurality of second-dimension sub-blocks by dividing the 2D array along a second dimension. In response to determining that second-dimension error correction code (ECC) encoding is enabled, the system performs second-dimension ECC encoding on the second-dimension sub-blocks to generate a set of second-dimension ECC bits and performs first-dimension ECC encoding on the first-dimension sub-blocks and the second-dimension ECC bits to generate a set of first-dimension ECC bits. The system writes the data block along with the second-dimension ECC bits and the first-dimension ECC bits to the storage device.

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

Abstract: Channel selection information indicate positions of data bits of input data, positions of error correction code (ECC) parity bits for correcting errors in the input data, and positions of state shaping parity bits. The ECC parity bits and the state shaping parity bits are generated to cause a decrease in a quantity of memory cells, of the plurality of memory cells, in which at least one target state among a plurality of states is programmed. An alignment vector is generated based on aligning the data bits of the input data, the ECC parity bits, and the state shaping parity bits, based on the channel selection information. A codeword is generated based on simultaneously performing state shaping and ECC encoding with respect to the alignment vector. Write data are written in the nonvolatile memory device based on the codeword.

Abstract: To improve throughput by reducing the resource used for transmitting a parameter relating to retransmission control and decreasing the overhead of retransmission control signaling. In a case where a retransmission control method is employed in consideration of adaptive MCS control in which the encoding rate can be changed, the scheduling section sets the MCS in accordance with CQI notified from the communication counterpart apparatus. When transmission data is encoded, the RV parameter bit-number setting section sets the number of bits used for signaling the RV parameter to decrease as the encoding rate of the first transmission is decreased and sets the RV parameter based on the number of bits. For example, in a case where the encoding rate R is R>2/3, two bits are set. In a case where the encoding rate 1/3<R?2/3, one bit is set. On the other hand, in a case where R?1/3, zero bits is set.

Abstract: An error recovery process provides for identifying a set of failed data blocks read from a storage medium during execution of a read command, populating sample buffers in a read channel with data of a first subset of the set of failed data blocks, and initiating an error recovery process on the data in the sample buffers. Responsive to successful recovery of one or more data blocks in the first subset, recovered data is released from the sample buffers and sample buffers locations previously-storing the recovered data are repopulated with data of a second subset of the set of failed data blocks. The error recovery process is then initiated on the data of the second subset of the failed data blocks while the error recovery process is ongoing with respect to data of the first subset of failed data blocks remaining in the sample buffers.

Abstract: Provided herein are method and apparatus for channel coding in the fifth Generation (5G) New Radio (NR) system. An embodiment provides an apparatus for a Next Generation NodeB (gNB), including circuitry, which is configured to: generate Downlink Control Information (DCI) payload for a NR-Physical Downlink Control Channel (NR-PDCCH); attach Cyclic Redundancy Check (CRC) to the DCI payload; mask the CRC with an Radio Network Temporary Identifier (RNTI) using a bitwise modulus 2 addition operation, wherein the number of bits for the RNTI is different from the number of bits for the CRC; and perform polar encoding for the DCI payload with the masked CRC.

Abstract: This application provides a polar code encoding method and apparatus. The method includes: obtaining, by a sending device, a sequence corresponding to a required mother code length; obtaining, by the sending device, a to-be-encoded bit; and performing, by the sending device, polar code encoding on the to-be-encoded bit by using the sequence corresponding to the required mother code length, to obtain an encoded bit, where the sequence is generated based on a basic sequence, and a length of the basic sequence is less than the mother code length.

Abstract: According to one general aspect, an apparatus may include a first power signal having a high voltage. The apparatus may include a second power signal having a low voltage. The apparatus may include a third power signal having a voltage configured to switch between the high voltage and the low voltage. The apparatus may include a latching circuit powered by the first power signal and the second power signal. The apparatus may include a selection circuit configured to select between, at least, a first data signal and a second data signal, and powered by the first power signal, the second power signal, and the third power signal.

Abstract: A method includes dispersed storage error encoding data to produce a plurality of sets of encoded data slices in accordance with dispersed storage error coding parameters. A plurality of identifiers corresponding to the plurality of sets of encoded data slices are determined, and integrity information is determined for the plurality of identifiers. The plurality of sets of encoded data slices, the plurality of identifiers, and the integrity information are sent to a distributed storage network memory for storage therein.

Abstract: A device for detecting an error of data stored in a memory device includes an error detection trigger circuit configured to transmit an error detection trigger information for instructing an error detecting operation for at least a part of the data, at each first cycle, in the case where an error detection performing condition is satisfied; an error detection performing circuit configured to receive the error detection trigger information, instruct an error calculation engine to perform an error detecting operation for part or all of the data, and receive an error detection result information from the error calculation engine; and a reporting circuit configured to transmit reporting information depending on the error detection result information, to a target device.

Abstract: Methods, apparatus, systems and procedures to manage a multicast communication to a multicast group implemented by a respective wireless transmit/receive unit (WTRU) of WTRUs in the multicast group are disclosed. One representative method includes receiving, by the respective WTRU of the multicast group, a configuration, the configuration indicating a Random Access Channel (RACH) preamble to use for a negative acknowledgement (NACK) response to a multicast transmission to the respective WTRU, monitoring, by the respective WTRU, for data of the multicast transmission, determining, by the respective WTRU, whether the monitored for data was successfully received; and on condition that the monitored for data was not successfully received, sending, by the respective WTRU, the RACH preamble indicated by the received configuration.