Abstract: A light-emitting device package according to an embodiment comprises lenses arranged in and on a light-emitting device. The lenses comprise an upper surface including a recessed part; a groove part arranged on one or more areas of the upper surface; a bottom surface facing the light-emitting device; a supporting part arranged on the bottom surface; and an outer surface that is slanted with respect to the bottom surface and that contacts the groove part, wherein the groove part is arranged more outwardly from the lens than the support part relative to the light-emitting device.

Abstract: A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer.

Abstract: A power semiconductor device includes a substrate of a first conductivity type, a buried layer of a second conductivity type formed in at least a portion of the substrate, and at least one epitaxial layer of the first conductivity type formed on at least a portion of an upper surface of the substrate and covering the buried layer. The epitaxial layer and the buried layer form a junction capacitor. The device further includes at least one active power transistor formed in an upper surface of the epitaxial layer and above at least a portion of the buried layer.

Abstract: A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.

Abstract: Various heterostructures and methods of forming heterostructures are disclosed. A method includes removing portions of a substrate to form a temporary fin protruding above the substrate, forming a dielectric material over the substrate and over the temporary fin, removing the temporary fin to form a trench in the dielectric material, the trench exposing a portion of a first crystalline material of the substrate, forming a template material at least partially in the trench, the template material being a second crystalline material that is lattice mismatched to the first crystalline material, forming a barrier material over the template material, the barrier material being a third crystalline material, forming a device material over the barrier material, the device material being a fourth crystalline material, forming a gate stack over the device material, and forming a first source/drain region and a second source/drain region in the device material.