Abstract: A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.

Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.

Abstract: A semiconductor structure includes a substrate, a plurality of fins disposed over a top surface of the substrate, and a gate stack surrounding a portion of sidewalls of the plurality of fins. The plurality of fins include two or more active device fins comprising a semiconducting material providing vertical transport channels for respective vertical transport field-effect transistors, and two or more edge fins surrounding the two or more active device fins, the two or more edge fins comprising a dielectric material. Thicknesses of one or more layers of the gate stack surrounding the portion of the sidewalls of the two or more edge fins are different than thicknesses of the one or more layers of the gate stack surrounding the portion of the sidewalls of the active device fins. The vertical transport field-effect transistors provided by the active device fins have uniform threshold voltage.

Abstract: A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.

Abstract: A light emitting device package can include first and second frames spaced apart from each other; a package body including a body portion disposed between the first and second frames; a light emitting device including first and second electrode pads; a first through hole in the first frame; a second through hole in the second frame; a conductive material disposed in the first and second through holes; and an intermetallic compound layer disposed between the conductive material and the first frame, and between the conductive material and the second frame, in which the first electrode pad of the light emitting device overlaps with the first through hole in the first frame, the second electrode pad of the light emitting device overlaps with the second through hole in the second frame, and the first and second electrode pads are spaced apart from each other.

Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first silicon nitride layer. The first region is covered with a protection layer that can be etched selectively with respect to the silicon nitride. The structure is covered with a second silicon nitride layer. The trenches are etched through the second and first silicon nitride layers and filled with a filling silicon oxide to a level situated above the protection layer. The second silicon nitride layer and the part of the first silicon nitride layer situated on the second region are selectively removed and the protection layer is removed. The filling oxide is selectively etched by wet etching, thus resulting in pits on the surface of the filling oxide around the second region.

Abstract: To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device includes an active region having resistance properties that can be modified to store one or more data bits in the resistive memory device, and at least one sidewall portion of the active region comprising a dopant configured to suppress conductance paths in the active region proximate to the at least one sidewall portion. The resistive memory device includes terminals configured to couple the active region to associated electrical contacts.

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

Abstract: A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.

Abstract: A tilted nanowire structure is provided which has an increased gate length as compared with a horizontally oriented semiconductor nanowire at the same pitch. Such a structure avoids complexity required for vertical transistors and can be fabricated on a bulk semiconductor substrate without significantly changing/modifying standard transistor fabrication processing.

Abstract: A side view surface mount light emitting device is disclosed. The light emitting device comprises a side oriented package comprising a floor and a plurality of light emitting diodes (LEDs) mounted on the floor. The device further includes a plurality of contact pins in electrical contact, such that the plurality of contact pins protrude from a side of the package, in which at least one of the contact pins is oriented in a direction opposite the remaining contact pins. The LEDs of the device are disposed to emit light in a direction parallel to said mount surface. Some configurations also include a plurality of bond pads, on or a part of the floor, to facilitate electrical connection between the LEDs and the contact pins, in which adjacent bond pads have a tapered shape such that the widest portion of a first bond pad is adjacent to the narrowest portion of a second bond pad. Displays including such devices are also disclosed.

Abstract: An organic light emitting diode device comprising: a light emitting layer or layers combining both an emissive material comprising a boron subphthalocyanine, or first emitting layer component, that emits substantially orange light; and an emissive material emitting blue light, or second emitting layer component; wherein in combination, the first emitting layer component and the second emitting layer component, in combination, produces an overall white or near-white light emission.

Abstract: A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Aspect ratio trapping is employed during fabrication of the transistor device on a silicon substrate. Homojunction and heterojunction devices are formed using III-V materials with appropriate bandgaps. The emitter of the device may be electrically connected by a lateral buried metal contact.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

Abstract: Semiconductor devices and fabrication methods are provided. A fabrication method includes: forming a source and drain material layer over a substrate; forming a mask layer over the source and drain material layer and including a first trench exposing a portion of the source and drain material layer; forming a protective layer on sidewalls of the first trench; forming a second trench in the source and drain material layer using the mask layer and the protective layer as an etch mask; removing the protective layer after the second trench is formed; forming a channel material layer and a gate structure on the channel material layer after the protective layer is removed; and removing the mask layer after the channel material layer and the gate structure are formed. The channel material layer is on the sidewalls and the bottom of the first trench and the second trench.

Abstract: A semiconductor device includes a substrate, a thermal conduction layer on the substrate, a first wire pattern on the thermal conduction layer, a first semiconductor pattern a second semiconductor pattern, and a gate electrode between the first semiconductor pattern and the second semiconductor pattern. The gate electrode surrounds a periphery of the first wire pattern. A concentration of impurity of the thermal conduction layer is different from that of the substrate. The first wire pattern includes a first end and a second end. The concentration of impurity contained in the first wire pattern is higher than that contained in the thermal conduction layer and that contained in the substrate. The first semiconductor pattern is in contact with the first end of the first wire pattern and the thermal conduction layer. The second semiconductor pattern is in contact with the second end of the first wire pattern.

Abstract: Provided are an optical apparatus, a manufacturing method of a distributed Bragg reflector laser diode, and a manufacturing method of the optical apparatus, the an optical apparatus including a cooling device, a distributed Bragg reflector laser diode having a lower clad including a recess region on one side of the cooling device and connected to another side of the cooling device, and an air gap between the cooling device and the distributed Bragg reflector laser diode, wherein the air gap is defined by a bottom surface of the lower clad in the recess region and a top surface of the cooling device.

Abstract: A semiconductor device includes a semiconductor element, a semiconductor substrate on which the semiconductor element is mounted, a conductive layer formed on the substrate, and a sealing resin covering the semiconductor element. The substrate is formed with a recess receding from a main surface of the substrate and including a bottom surface and first and second sloped surfaces spaced apart from each other in a first direction perpendicular to the thickness direction of the substrate. The conductive layer includes first conduction paths on the first sloped surface, second conduction paths on the second sloped surface and bottom conduction paths on the bottom surface. The second sloped surface includes exposed regions line-symmetrical to the first conduction paths with respect to a line perpendicular to both the thickness direction of the substrate and the first direction, and the second conduction paths are not disposed at the exposed regions.

Abstract: A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.