Abstract: Disclosed is a method. The method includes forming a trench structure with at least one first trench in a first section of a semiconductor body; forming a second trench that is wider than the first trench in a second section of the semiconductor body; and forming a semiconductor layer on a surface of the semiconductor body in the first section and the second section and in the at least one first trench and the second trench such that the semiconductor layer has a substantially planar surface above the first section and a residual trench remains above the second section. Forming the semiconductor layer includes forming a first epitaxial layer in a first epitaxial growth process and a second epitaxial layer on top of the first epitaxial layer in a second epitaxial growth process.

Abstract: A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.

Abstract: An optical apparatus includes a cooling device with a lower clad disposed thereon; a waveguide disposed on the lower clad and including an active waveguide to define a gain section and a passive waveguide to define a wavelength-tunable section; gratings disposed in the lower clad of the wavelength-tunable section; an upper clad disposed on the waveguide; a first upper electrode disposed on the upper clad of the gain section; and a second upper electrode disposed on the upper clad of the wavelength-tunable section. The lower clad of the wavelength-tunable section has a recess region to expose an upper surface of the cooling device, the recess region forming an air gap-having a height of 10 ?m to 80 ?m from the upper surface of the cooling device. The gratings are formed in a depth of at least 5 ?m from a bottom surface of the lower clad of the recess region.

Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.

Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

Abstract: An array substrate, a display panel and a display device are disclosed. The array substrate includes a base substrate and a plurality of pixel unit. Each of the pixel unit includes a thin-film-transistor, and the thin-film-transistor includes a gate electrode and a drain electrode; the drain electrode includes a first drain electrode portion, a second drain electrode portion and a first connection portion; and an orthographic projection of the first drain electrode portion on the base substrate and an orthographic projection of the gate electrode on the base substrate are spaced apart, and an orthographic projection of the second drain electrode portion on the base substrate and the orthographic projection of the gate electrode on the base substrate at least partially overlap.

Abstract: A semiconductor device that includes a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer includes a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of at least two suspended channel structures. The inner spacer may be composed of an n-type or p-type doped glass.

Abstract: A semiconductor device provided in a pixel circuit of a display device includes, in order from a lower side: a substrate; an LTPS layer; a first gate insulating layer; a first metal layer; a first flattened layer; a second gate insulating layer; an oxide semiconductor layer; a second metal layer; a passivation layer; and a third metal layer. The gate electrode layer of an LTPS-TFT and the gate electrode of an oxide semiconductor TFT are formed by the first metal layer.

Abstract: A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Aspect ratio trapping is employed during fabrication of the transistor device on a silicon substrate. Homojunction and heterojunction devices are formed using III-V materials with appropriate bandgaps. The emitter of the device may be electrically connected by a lateral buried metal contact.

Abstract: There is provided a semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer using a hybrid interlayer insulating film. The semiconductor device includes a gate electrode on a substrate, a gate spacer being on a sidewall of the gate electrode and including an upper portion and a lower portion, a lower interlayer insulating film being on the substrate and overlapping with the lower portion of the gate spacer, and an upper interlayer insulating film being on the lower interlayer insulating film and overlapping with the upper portion of the gate spacer, wherein the lower interlayer insulating film is not interposed between the upper interlayer insulating film and the upper portion of the gate spacer.

Abstract: A light emitting diode chip including a light emitting structure having an active layer, and a distributed Bragg reflector (DBR) disposed to reflect light emitted therefrom. The DBR has first and second regions, and a third region therebetween. The first region is closer to the light emitting structure than the second and third regions. The DBR includes first material layers having a high index of refraction and second material layers having a low index of refraction alternately disposed one over another. The first material layers include first, second, and third groups having an optical thickness greater than 0.25?+10%, in a range of 0.25??10% to 0.25?+10%, and less than 0.25??10%, respectively. With respect to a central wavelength (?: 554 nm) of the visible range, the first region has the first and second groups, the second region has the third group, and the third region has the second and third groups.

Abstract: An SOI substrate manufacturing method and an SOI substrate are provided, where the method includes: forming a patterned etch-stop layer in an oxide layer of a first silicon substrate, bonding a surface, having the patterned etch-stop layer (130), of the first silicon substrate with a surface of a second silicon substrate, and peeling off a part of the first silicon substrate to form a patterned SOI substrate.

Abstract: A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.

Abstract: An electronics device with at least one component to be cooled, a cooling element for cooling the component to be cooled, at least one power supply line, and a respective current sensor for recording a current strength of a current flowing through the respective power supply line, wherein the cooling element has a recess, in which the current sensor engages or in which the current sensor is arranged.

Abstract: A semiconductor device includes an electrical device and has an output capacitance characteristic with at least one output capacitance maximum located at a voltage larger than 5% of a breakdown voltage of the semiconductor device. The output capacitance maximum is larger than 1.2 times an output capacitance at an output capacitance minimum located at a voltage between the voltage at the output capacitance maximum and 5% of a breakdown voltage of the semiconductor device.

Abstract: A method for forming an integrated circuit (IC) and an IC are disclosed. The method for forming the IC includes: forming an isolation structure separating a memory semiconductor region from a logic semiconductor region; forming a memory cell structure on the memory semiconductor region; forming a memory capping layer covering the memory cell structure and the logic semiconductor region; performing a first etch into the memory capping layer to remove the memory capping layer from the logic semiconductor region, and to define a slanted, logic-facing sidewall on the isolation structure; forming a logic device structure on the logic semiconductor region; and performing a second etch into the memory capping layer to remove the memory capping layer from the memory semiconductor, while leaving a dummy segment of the memory capping layer that defines the logic-facing sidewall.

Abstract: A photo-sensitive device includes a uniform layer, a gradated buffer layer over the uniform layer, a silicon layer over the gradated buffer layer, a photo-sensitive light-sensing region in the uniform layer and the silicon layer, a device layer on the silicon layer, and a carrier wafer bonded to the device layer.

Abstract: A semiconductor device includes: a substrate; a first source/drain region and a second source/drain region spaced apart from each other by a trench in the substrate; and a gate structure in the trench, wherein the gate structure includes: a gate dielectric layer formed on a bottom and sidewalls of the trench; a first gate electrode positioned in a bottom portion of the trench over the gate dielectric layer; a second gate electrode positioned over the first gate electrode; and a dipole inducing layer formed between the first gate electrode and the second gate electrode and between sidewalls of the second gate electrode and the gate dielectric layer.

Abstract: A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer.

Abstract: A method of fabricating an LED includes: providing an epitaxial structure having a growth substrate, a first-type semiconductor layer, an active layer and a second-type semiconductor layer; forming an extended electrode and performing thermal treatment to form ohmic contact with the second-type semiconductor layer; providing a temporary substrate bonded with the epitaxial structure, and removing the growth substrate to expose the surface of the first-type semiconductor layer; forming an ohmic contact layer, a mirror layer and a bonding layer over the exposed surface of the first-type semiconductor layer; providing a conductive substrate bonded with the bonding layer, and removing the temporary substrate to expose part of the surface of the second-type semiconductor layer and the extended electrode; forming a roughening surface via etching of the exposed second-type semiconductor layer; and providing a bonding wire electrode forming a closed loop with the extended electrode.