Abstract: This disclosure relates to light emitting devices and methods of manufacture thereof, including side and/or multi-surface light emitting devices. Embodiments according to the present disclosure include the use of a functional layer, which can comprise a stand-off distance with one or more portions of the light emitter to improve the functional layer's stability during further device processing. The functional layer can further comprise winged portions allowing for the coating of the lower side portions of the light emitter to further interact with emitted light and a reflective layer coating on the functional layer to further improve light extraction and light emission uniformity. Methods of manufacture including methods utilizing virtual wafer structures are also disclosed.

Abstract: A device and techniques for fabricating the device are described for forming a wafer-level thermal sensor package using microelectromechanical system (MEMS) processes. In one or more implementations, a wafer level thermal sensor package includes a thermopile stack, which includes a substrate, a dielectric membrane, a first thermoelectric layer, a first interlayer dielectric, a second thermoelectric layer, a second interlayer dielectric, a metal connection assembly, a passivation layer, where the passivation layer includes at least one of a trench or a hole, and where the substrate includes a cavity adjacent to the at least one trench or hole, and a bond pad disposed on the passivation layer and electrically coupled to the metal connection assembly; and a cap wafer assembly coupled to the thermopile stack, the cap wafer assembly including a wafer having a cavity formed on a side of the wafer configured to be adjacent to the thermopile stack.

Abstract: A first S/D region includes a first P-type region, a first N-type region, and a first conductive layer thereon to define a first cell node. A second S/D region includes a second P-type region, a second N-type region, and a second conductive layer thereon to define a second cell node. A PDL transistor and PGLA, PGLB transistors have bottom SD regions in the first N-type region. A PUL transistor has a bottom SD region positioned in the first P-type region. A PDR transistor and PGRA, PGRB have bottom SD regions in the second N-type region. A PUR transistor has a bottom SD region in the second P-type region. A first gate is positioned around channel regions of the PUL and PDL transistors and conductively coupled to the second node. A second gate is positioned around channel regions of the PUR and PDR transistors and conductively coupled to the first node.

Abstract: A light emitting device includes an epitaxial structure. The epitaxial structure includes a first type semiconductor layer, a second type semiconductor layer and a light emitting layer. The first type semiconductor layer includes a first semiconductor sublayer. The light emitting layer is disposed between the first type semiconductor layer and the second type semiconductor layer. The first semiconductor sublayer includes a heavily doped part and a lightly doped part which are doped by a first type dopant. A doping concentration of the first type dopant in the heavily doped part is equal to 1018 atoms/cm3 or between 1017 atoms/cm3 and 1018 atoms/cm3. A doping concentration of the first type dopant in the lightly doped part is less than or equal to 1017 atoms/cm3.

Abstract: A system and methods for analyzing seismic data are provided herein. The method includes identifying, via a computing device, a representation of a seismic data set (1802) and determining a number of feature descriptors corresponding to each of a number of aggregates within the representation (1804). The method also includes identifying a query relating to the representation and one or more vocabulary definitions relating to the query (1806), analyzing the representation to compute a likelihood that each of the aggregates satisfies the query (1808), and returning a result of the query (1810).

Abstract: A dual-sided display is disclosed, including a substrate, a first active device, a first micro light emitting device, a patterned photoresist layer, a reflective electrode, a second micro light emitting device, a protective layer, and a first conductive electrode. The first micro light emitting device is disposed on the substrate and electrically connected to the first active device. The patterned photoresist layer is disposed on the substrate and covers a portion of the first micro light emitting device. The reflective electrode covers the patterned photoresist layer and a portion of the substrate. The second micro light emitting device is disposed on the reflective electrode. The protective layer covers the reflective electrode and a portion of the second micro light emitting device. The first conductive electrode covers the protective layer and is electrically connected to the second micro light emitting device.

Abstract: A field effect transistor includes a substrate and a gate dielectric formed on the substrate. A channel material is formed on the gate dielectric. The channel material includes carbon nanotubes. A patterned resist layer has openings formed therein. The openings expose portions of the gate dielectric and end portions of the channel material under the patterned resist layer. Metal contacts are formed at least within the openings. The metal contacts include a portion that contacts the end portions of the channel material and the portions of the gate dielectric exposed within the openings.

Abstract: A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.

Abstract: A light emitting diode, the light emitting diode including: a first semiconductor layer, an active layer, a second semiconductor layer, wherein a surface of the second semiconductor layer defines a first area; a metallic plasma generating layer; a first electrode; a second electrode; wherein the metallic plasma generating layer includes a plurality of three-dimensional nanostructures, the three-dimensional nanostructure includes a first rectangular structure, a second rectangular structure, and a triangular prism structure, the first rectangular structure, the second rectangular structure, and the triangular prism structure are stacked, the width of the triangular prism structure is equal to the width of the second rectangular structure, and is greater than the width of the first rectangular structure, the first rectangular structure is a metal layer, and the triangular prism structure is a metal layer.

Abstract: To prevent an intermediate region from contacting a cathode electrode even if a cathode region is partially defective. There is provided a semiconductor device with a semiconductor substrate that has a field stop region where first impurities of a first conduction type are implanted, an intermediate region that is formed on a back surface side of the field stop region and where second impurities of a second conduction type are implanted, and a cathode region of the first conduction type that is formed on a back surface side of the intermediate region. In a back surface of the semiconductor substrate, a concentration of the first impurities is higher than a concentration of the second impurities.

Abstract: An HVJT is includes a parasitic diode formed by pn junction between an n?-type diffusion region and a second p?-type separation region surrounding a periphery thereof. The n?-type diffusion region is arranged between an n-type diffusion region that is a high potential side region and an n-type diffusion region that is a low potential side region, and electrically separates these regions. In the n?-type diffusion region, an nchMOSFET of a level-up level shift circuit is arranged. The n?-type diffusion region has a planar layout in which the n?-type diffusion region surrounds a periphery of the n-type diffusion region and a region where the nchMOSFET is arranged protrudes inwardly. A high-concentration inter-region distance L1 of the nchMOS region where the nchMOSFET is arranged is longer than a high-concentration inter-region distance L2 of the parasitic diode. Thus, the reliability of the semiconductor device may be improved.

Abstract: After forming source/drain contact openings to expose portions of source/drain regions composed of an n-doped III-V compound semiconductor material, surfaces of the exposed portions of the source/drain regions are cleaned to remove native oxides and doped with plasma-generated n-type dopant radicals. Semiconductor caps are formed in-situ on the cleaned surfaces of the source/drain regions, and subsequently converted into metal semiconductor alloy regions. Source/drain contacts are then formed on the metal semiconductor alloy regions and within the source/drain contact openings.

Abstract: An energy-efficient industrial sensor is provided that optimizes power consumption based on characteristics of the requirements of the sensing application in which the sensor is used. Operating parameters of the sensor, such as sensing range, operating frequency, response time, noise immunity, or other such parameters, can be scaled to suit the sensing and response requirements and environmental conditions of the sensing application. This allows the sensor to consume less energy when used in sensing applications that do not require peak sensor performance. In some embodiments, the sensor can measure the environmental or machine operating conditions in its immediate vicinity and dynamically scale its operating parameters based on the measured information. By down-scaling the sensor's operating parameters from their maximum performance levels where appropriate, the overall energy footprint of a network of sensors can be reduced.

Abstract: A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.

Abstract: A method of manufacturing a semiconductor device is presented. The method includes providing a semiconductor layer comprising silicon carbide, wherein the semiconductor layer comprises a first region doped with a first dopant type. The method further includes implanting the semiconductor layer with a second dopant type using a single implantation mask and a substantially similar implantation dose to form a second region and a junction termination extension (JTE) in the semiconductor layer, wherein the implantation dose is in a range from about 2×1013 cm?2 to about 12×1013 cm?2. Semiconductor devices are also presented.

Abstract: A high-voltage transistor (HVT) structure adapts a low-voltage transistor (LUT) to high-voltage environments. The HVT structure includes a drain node, a source node, a control gate, and a field electrode. The drain node and the source node define a conductive channel, in which mobilized charges are regulated by the control gate. While being isolated from the control gate, the field electrode is configured to spread the mobilized charges in response to a field voltage. The field electrode is structured and routed to prevent charge sharing with any one of the drain node, source node, or control gate. Advantageously, the isolated field electrode minimizes the capacitance of the control gate as well as the drain and source nodes, such that the HVT can switch with less power loss and a more robust performance in a high-voltage environment.

Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.

Abstract: A light-emitting device includes a substrate including an upper surface; a light-emitting stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the light-emitting stack includes a first surface and a second surface opposite to the first surface toward to the upper surface; a plurality of depressions formed in the light-emitting stack and penetrating the second semiconductor layer, the active layer and a portion of the first semiconductor layer; an insulative layer covering the second surface of the light-emitting stack; a connector including a first portion and a second portion; and an electrode disposed at a side of the light-emitting stack and electrically connecting the connector, wherein the first portion of the connector is formed in the plurality of depressions, the second portion of the connector is between the insulative layer and the light-emitting stack.

Abstract: A semiconductor device capable of reducing an inter-source electrode resistance RSS (on) and reducing a chip size is provided. A semiconductor device according to the present invention includes a chip partitioned into three areas including a first area, a second area, and a third area, and a common drain electrode provided on a back surface of the chip, in which the second area is formed between the first and third areas, a first MOSFET is formed in the first area and the third area, and a second MOSFET is formed in the second area.

Abstract: Position data interpolation unit interpolates 3D coordinate values or rotation angles, for periods of time, at each interpolation position on line segments that connect adjacently installed sensors, based on 3D coordinate values or rotation angles of the respective installation positions of the plurality of sensors measured by the measurement unit. A coordinate conversion unit computes 3D coordinate values of each position corresponding to a 3D shape of the measurement target object at periods of time, based on 3D coordinate values or rotation angles of the respective installation positions of the plurality of sensors measured at periods of time, based on 3D coordinate values or rotation angles of each of the interpolation positions on line segments that connect sensors interpolated at periods of time, and based on relative distances between the adjacently installed sensors along deformed shape of the measurement target object.