Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.

Abstract: In an embodiment, a method includes: connecting a light emitting diode to a substrate; encapsulating the light emitting diode with a photosensitive encapsulant; forming a first opening through the photosensitive encapsulant adjacent the light emitting diode; and forming a conductive via in the first opening.

Abstract: One of embodiments is a method of manufacturing driven element chips by dividing a semiconductor wafer into the driven element chips. The method includes preparing a semiconductor wafer which includes chip substrate portions arrayed in an array direction, and a clearance between the chip substrate portions adjacent to each other in the array direction. Each chip substrate portion includes: a conductive layer provided inside the chip substrate portion and including interconnect portions; and a dummy conductor provided in a part of the conductive layer where the interconnect portions are not provided.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

Abstract: An organic light emitting diode device comprising: a light emitting layer or layers combining both an emissive material comprising a boron subphthalocyanine, or first emitting layer component, that emits substantially orange light; and an emissive material emitting blue light, or second emitting layer component; wherein in combination, the first emitting layer component and the second emitting layer component, in combination, produces an overall white or near-white light emission.

Abstract: Solid-state light emitting devices including light-emitting diodes (LEDs), and more particularly packaged LEDs that include individually controllable LED chips are disclosed. In some embodiments, an LED package includes electrical connections configured to reduce corrosion of metals within the package; or decrease the overall forward voltage of the LED package; or provide an electrical path for electrostatic discharge (ESD) chips. In some embodiments, an LED package includes an array of LED chips, each of which is individually controllable such that individual LED chips or subgroups of LED chips may be selectively activated or deactivated. A single wavelength conversion element may be provided over the array of LED chips, or separate wavelength conversion elements may be provided over one or more individual LED chips of the array. Representative LED packages may be beneficial for applications where a high luminous intensity with a controllable brightness or adaptable emission pattern is desired.

Abstract: A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A sandwich gate dielectric layer structure is disposed on the second active layer. A passivation layer is disposed over the sandwich gate dielectric layer structure. A gate extends through the passivation layer to the sandwich gate dielectric layer structure. First and second ohmic contacts electrically connected to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.

Abstract: Embodiments of the present invention are directed to techniques for integrating a split gate metal-oxide-nitride-oxide-semiconductor (SG-MONOS) memory with a vertical field effect transistor (VFET). In a non-limiting embodiment of the invention, a vertical SG-MONOS memory device is formed on a first region of a substrate. The SG-MONOS memory device can include a charge storage stack, a memory gate on the charge storage stack, and a control gate vertically stacked over the charge storage stack and the memory gate. A VFET is formed on a second region of the substrate. The VFET can include a logic gate.

Abstract: Methods form devices by creating openings in sacrificial gates between nanosheet stacks (alternating layers of a first material and channel structures), forming spacers in the openings, and removing the sacrificial gates to leave the spacers. The first material is then removed from between the channel structures. A first work function metal is formed around and between the channel structures. Next, first stacks (of the stacks) are protected with a mask to leave second stacks (of the stacks) exposed. Then, the first work function metal is removed from the second stacks while the first stacks are protected by the mask and the spacers. Subsequently, a second work function metal is formed around and between the channel structures of the second stacks. A gate material is then formed over the first work function metal and the second work function metal.

Abstract: A pixel arrangement structure is disclosed. The structure includes multiple first pixel rows and multiple second pixel rows arranged alternately. Wherein each of the first pixel rows includes multiple first sub-pixels and multiple second sub-pixels disposed alternately and at intervals, and each of the second pixel rows includes multiple third sub-pixels disposed at intervals. Wherein the first sub-pixel and the second sub-pixel adjacent to the third sub-pixel form a virtual triangle, the third sub-pixel is disposed in the virtual triangle formed by the first sub-pixel and the second sub-pixel adjacent to the third sub-pixel. Applying the pixel arrangement structure to an OLED display panel can improve the resolution, reduce the fabrication difficulty, increase the pixel area, and improve the brightness and life of the OLED display panel.

Abstract: A method of manufacturing a flip-chip light emitting diode includes: providing a transparent substrate and a temporary substrate, and bonding the transparent substrate with the temporary substrate; grinding and thinning the transparent substrate; providing a light-emitting epitaxial laminated layer having a first surface and a second surface opposite to each other, and including a first semiconductor layer, an active layer and a second semiconductor layer; forming a transparent bonding medium layer over the first surface of the light-emitting epitaxial laminated layer, and bonding the transparent bonding medium layer with the transparent substrate; defining a first electrode region and a second electrode region over the second surface of the light-emitting epitaxial laminated layer, and manufacturing a first electrode and a second electrode; and removing the temporary substrate.

Abstract: Semiconductor devices and fabrication methods are provided. A semiconductor device includes a substrate, a source and drain material layer formed on the substrate. The source and drain material layer contains a first trench there-through. The semiconductor device further includes a mask layer formed on the source and drain material layer containing a second trench there-through. The second trench has a cross-section area larger than the first trench and covers the first trench. The semiconductor device further includes a channel material layer conformally formed on a bottom and sidewalls of each of the first trench and the second trench and a gate structure conformally formed on the channel material layer, on the bottom and the sidewalls of each of the first trench and the second trench. The gate structure has a recess and the recess has a symmetrical step structure.

Abstract: A light emitting device includes a plurality of light emitting elements each including a light extraction surface, a plurality of phosphor layers each covering the light extraction surface of a corresponding one of the light emitting elements with a larger plane area than the light extraction surface, and a plurality of light transmissive members. Each of the light transmissive members has a lower surface facing a corresponding one of the phosphor layers and having a larger plane area than the light extraction surface of a corresponding one of the light emitting elements, an upper surface having a larger plane area than the lower surface, and a side surface having a vertical surface portion contiguous with the upper surface. The light reflecting member surrounds the side surface of each of the light transmissive members.

Abstract: A method for forming an integrated circuit (IC) and an IC are disclosed. The method for forming the IC includes: forming an isolation structure separating a memory semiconductor region from a logic semiconductor region; forming a memory cell structure on the memory semiconductor region; forming a memory capping layer covering the memory cell structure and the logic semiconductor region; performing a first etch into the memory capping layer to remove the memory capping layer from the logic semiconductor region, and to define a slanted, logic-facing sidewall on the isolation structure; forming a logic device structure on the logic semiconductor region; and performing a second etch into the memory capping layer to remove the memory capping layer from the memory semiconductor, while leaving a dummy segment of the memory capping layer that defines the logic-facing sidewall.

Abstract: The invention describes a method of manufacturing an OLED device (1) comprising an OLED (10) and an integrated negative overvoltage protection diode (11), which method comprises at least the steps of: depositing a first OLED electrode (100) and a separate second OLED electrode contact (101C) on a carrier (12), which second OLED electrode contact (101C) incorporates a first overvoltage protection diode electrode (110); depositing an organic material layer stack (14) to define an active region (14OLED) of the OLED (10) and an active region (14OPD) of the overvoltage protection diode (11); depositing a second OLED electrode (101) to extend over the active region (14OLED) of the OLED (10) and the second OLED electrode contact (101C); and depositing a second overvoltage protection diode electrode (111) to extend over the active region (14OPD) of the overvoltage protection diode (11) and the first OLED electrode (100).

Abstract: Molecular Graphene (MG) of a physical size and bonding character that render the molecule suitable as a channel material in an electronic device, such as a tunnel field effect transistor (TFET). The molecular graphene may be a large polycyclic aromatic hydrocarbon (PAH) employed as a discrete element, or as a repeat unit, within an active or passive electronic device. In some embodiments, a functionalized PAH is disposed over a substrate surface and extending between a plurality of through-substrate vias. Heterogeneous surfaces on the substrate are employed to direct deposition of the functionalized PAH molecule to surface sites interstitial to the array of vias. Vias may be backfilled with conductive material as self-aligned source/drain contacts. Directed self-assembly techniques may be employed to form local interconnect lines coupled to the conductive via material. In some embodiments, graphene-based interconnects comprising a linear array of PAH molecules are formed over a substrate.

Abstract: The present disclosure relates to the technical field of semiconductors, and in particular to a semiconductor chip, a semiconductor wafer and a method for manufacturing a semiconductor wafer. The semiconductor chip comprises: a substrate, devices provided on a side of the substrate, via holes running through the substrate, conductive material filled in the via holes and contacted with the devices, and a backside metal layer provided on the other side of the substrate away from the devices, the backside metal layer coming into contact with the conductive material so as to be electrically connected to the devices via the conductive material. The semiconductor chip, the semiconductor wafer and the method for manufacturing a semiconductor wafer of the present disclosure reduce the ground resistance and improve the heat dissipation of devices with via holes structure during the operation.

Abstract: A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure and an S/D contact structure formed over the fin structure. The FinFET device structure also includes an S/D conductive plug formed over the S/D contact structure, and the S/D conductive plug includes a first barrier layer and a first conductive layer. The FinFET device structure includes a gate contact structure formed over the gate structure, and the gate contact structure includes a second barrier layer and a second conductive layer. The FinFET device structure includes a first isolation layer surrounding the S/D conductive plug, and the first barrier layer is between the first isolation layer and the first conductive layer. A second isolation layer surrounding the gate contact structure, and the second barrier layer is between the second isolation layer and the second conductive layer.

Abstract: Disclosed is a method. The method includes forming a trench structure with at least one first trench in a first section of a semiconductor body; forming a second trench that is wider than the first trench in a second section of the semiconductor body; and forming a semiconductor layer on a surface of the semiconductor body in the first section and the second section and in the at least one first trench and the second trench such that the semiconductor layer has a substantially planar surface above the first section and a residual trench remains above the second section. Forming the semiconductor layer includes forming a first epitaxial layer in a first epitaxial growth process and a second epitaxial layer on top of the first epitaxial layer in a second epitaxial growth process.