Abstract: A method and apparatus for masking processor requests to improve bus efficiency includes a bus bridge having a detection logic for determining when a first processor on a first bus has been backed off the first bus a predetermined number of times. When the detection logic determines the first processor has been backed off the first bus the predetermined number of times, a timer is set to a first value, with the first value being sufficient to allow an agent on a second bus to access the first bus. A masking logic, coupled to the detection logic and the timer, is for masking requests from the first processor until the timer expires.

Abstract: Disclosed is a bus bridge for mutually connecting a memory bus having memories connected thereto and an I/O bus having plural I/O devices connected thereto, which comprises a conversion table in which pairs of entry and physical address are included and which is divided into a fixed part and a refillable part; an address conversion means for converting a logical address supplied from the I/O device to a physical address supplied to the memory, while selectively using the fixed part or the refillable part in accordance with whether the logical address is in address remapping space or in I/O-TBL space; and refilling means for refilling the contents of the refillable part from a mother address conversion table on a memory in case that the logical address is in the I/O-TBL space and the entry corresponding to the logical address does not exist in the refillable part.

Abstract: A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.

Abstract: A data-analyzing unit monitors and/or analyzes events on an information bus. The data-analyzing unit comprises an event recognition unit with one or more comparators coupled to the information bus and a sequencer state machine for determining sequential dependencies of events, whereby a state of the sequencer state machine depends on the history of information as provided thereto. The data-analyzing unit preferably comprises one or more counters coupled to the event recognition unit, thus allowing an analysis of data and/or events on the information bus. The data-analyzing unit may also comprise one or more memories coupled to the event recognition unit, thus providing a trace memory. In a preferred embodiment, the event recognition unit of the data-analyzing unit provides customized rules for monitoring defined event sequences of event behaviors thus allowing the monitoring of defined event sequences of event behaviors and possibly the drawing of conclusions therefrom e.g.

Abstract: A host module (2) including a host CPU (10) and a configurable expansion bus controller (28, 28', 128) is disclosed. The expansion bus controller (28, 28', 128) is configurable by way of configuration signals (BCFG) to be operable in various bus configurations for communicating signals between a module bus (IBUS) and external buses (XPCI1, XPCI0). These modes include combining the external buses (XPCI1, XPCI0) into a single bus of the 64-bit PCI type, operating the external buses (XPCI1, XPCI0) as separate 32-bit PCI buses, as separate CardBus buses, as separate AGP buses (either at one or multiple data transfers per cycle), or as combinations thereof. Certain of the configuration signals (BCFG) are used to select the clock frequencies at which the external buses (XPCI1, XPCI0) operate, in either of the 64-bit or 32-bit PCI protocols, or in the AGP bus protocol when present.

Abstract: A computer system includes a bus, a first bus device, a core circuit and a second circuit. The first bus device is coupled to the bus and adapted to finish a first indication of data to a portion of a bus beginning at a first clock cycle. The bus is capable of skewing the first indication to produce a second indication of the data at another portion of the bus beginning at another clock cycle. The second circuit is coupled to the bus and is adapted to receive an indication of a selected latency time. The second circuit is also adapted to transfer the data to the core circuit in response to the second indication and regulate the transfer so that the circuit receives the data beginning at the selected latency time after the first clock cycle.

Abstract: A bridge device for delivering data transactions between devices on two data buses in a computer system includes, for each pair of devices that may transact across the bridge device, a dedicated storage area that aids in completing transactions between the devices in the pair. The bridge device also includes a controller that allows transactions in one dedicated storage area to be completed without regard to the completion of earlier-issued transactions in another dedicated storage area.

Abstract: Circuits, systems, and methods relating to operating a computer system operable in a system manager mode (24). The method includes various steps. The first step (34) occurs during operation of the computer system (10) at a time other than start-up, and receives user power management data from a user of the computer system. The second step (38) stores the user power management data in memory space (30) accessible by the system management mode. The third step (40) accesses the user power management data from the memory space. Finally, the fourth step (42) controls at least one peripheral (14, 16, 18, 20) of the computer system in response to the accessed user power management data.

Abstract: A computing system that incorporates the invention includes a host processor which is coupled to a memory subsystem via a first bus system, a controller device and a second bus system. The controller device includes memory for storing plural Scripts for replay to the host processor, for instance, via the second bus system. A Script is an instruction set used to execute operations on a controller device. Each Script includes one or more addresses where either message or status data (or other operational data) can be found which is to be inserted, prior to dispatch of the Script. During operation of the computing system, the memory subsystem is caused, as a result of its operation, to issue an instruction to the controller device to dispatch a Script to, for instance, the host processor. The controller device responds by accessing the required Script, playing the Script which results in accesses to locally stored operational data for inclusion into the Script.

Abstract: The system and method for operating a cache-coherent shared-memory multiprocessing system is disclosed. The system includes a number of devices including processors, a main memory, and I/O devices. Each device is connected by means of a dedicated point-to-point connection or channel to a flow control unit (FCU). The FCU controls the exchange of data between each device in the system by providing a communication path between two devices connected to the FCU. The FCU includes a snoop signal path for processing transactions affecting cacheable memory and a network of signal paths that are used to transfer data between devices. Each signal path can operate concurrently thereby providing the system with the capability of processing multiple data transactions simultaneously.

Abstract: A power estimator calculates the total power consumption of a microprocessor having a CPU 5, a main memory 1 and a plurality of cache memories 2, 3 and 4 based on an assembler description of a program and calculates power consumption values when an instruction to be executed by the CPU 5 is read from a main memory 1 and when an instruction is read from the cache memories 2, 3 and 4, determines whether the instruction to be executed is read from a memory and then calculates the total power consumption for the microprocessor by using power consumption values for the memories based on the result and the power consumption value obtained for each memory.

Abstract: A computer system is presented having a mechanism for re-configuring the size of a data bus which links memory and/or input/output devices, or which links those devices to an execution unit. The mechanism includes a microcontroller embodying an chip select unit and a bus interface unit. The chip select unit allows computer system initiation from an upper memory address space occupied by a ROM. Thereafter, middle and lower memory address spaces occupied by RAM can be accessed by either an 8-bit or a 16-bit data bus, that data bus being either separate from or multiplexed with an address bus. The size of RAM can be configured in accordance with the data bus size which accesses RAM. Input/output address space can also be adjusted depending upon the data bus size which accesses input/output peripherals.

Abstract: An audio power management system for a computer to eliminate noise signals associated with the power-down and power-up operations of the computer during power management operations is disclosed. The audio power management system asserts a speaker mute signal before power is removed from the amplifier to reduce transient conditions. During power up, the speaker mute signal is applied to the amplifier for a period after power is applied to the amplifier. This control is done from a single digital output.

Abstract: A data processor is provided with a data input mode and a data output mode. The data input mode is set by an external signal. A serial data supplied from an external apparatus to a data input register has a signal to specify the start of the operation at its specific bit. The data processor is provided with a circuit which starts to operate by the operation start signal. This circuit generates an operation completion signal. Based on the operation completion signal, the mode of the data processor is automatically changed to the data output mode.

Abstract: A bus bridge circuit having an internal loopback capability involving a shared memory interface integrated therewith. The bridge circuit of the present invention includes a primary PCI interface, a secondary PCI interface, and a shared memory interface. Transfer between the primary and secondary interfaces may proceed in parallel with transfers between the secondary interface and the shared memory interface. A single master device on the primary bus may perform loopback testing of the bridge circuit by directing downstream transactions between the primary interface and the shared memory interface via the secondary interface. Configuration parameters of the bridge circuit permit the address range of the shared memory interface to temporarily overlap the address range of the secondary interface. The primary bus master device configures such an overlapping range and directs transactions to the secondary interface in the overlapping address range.

Abstract: A method and system is provided for avoiding data bus contention between EDO DRAM banks during a burst cycle to a memory page crossing a memory bank boundary. Each memory bank has output drivers configured to selectively drive data on a common data bus. The disclosed method and system contemplate decoding memory addresses into bank select signals and comparing the bank select signals for the current memory cycle to the state of the bank select signals in the previous cycle. If the current access is to a different bank, then the cycle is delayed and a disable signal is pulsed active to the EDO DRAM, disabling the output drivers. The memory page is kept open in the memory banks to allow bursts across bank boundaries. The current cycle is then allowed to continue to completion and data bus contention is avoiding while crossing the bank boundary.

Abstract: In an electronic apparatus having a plurality of printed boards or modules, an on-line module replacement system for allowing the desired of the boards to be inserted or removed while maintaining connecting lines alive allows a plug-in package to be mounted to a backboard without affecting the power supply voltage of other packages. This can be done without resorting to an inductance or similar impedance part heretofore included in a plug-in package.

Abstract: A priority queue structure and algorithm for managing the structure which in most cases performs in constant time. In other words, most of the time the inventive algorithm performs its work in an amount of time that is independent on the number of priority classes or elements that exist in the queue. The queue itself consists of a linked list of elements ordered into subqueues corresponding to priority classes, with higher priority subqueues appearing earlier in the queue. An array of priority pointers contains an entry for each subqueue that points to the last element of each subqueue. Elements are removed for processing from the top of the queue. Removal takes constant time. Items are inserted into an appropriate subqueue by linking it at the end of its respective subqueue.

Abstract: A repeater which introduces a minimum of delay in the transfer of a data packet from a source LAN to a destination LAN has an arbiter which grants access to a bus for a port to broadcast a received data packet onto the bus for loading the data packet into a transmit buffer for each outgoing port. The arbiter grants access only after all ports signal that their transmit buffers are ready to load the data packet from the bus. A transmit buffer signals that it is ready to be loaded at the passage of the collision window as it is transmitting a packet previously loaded into the transmit buffer. Accordingly, the transmit buffer is simultaneously transmitting the previously loaded packet and loading the new packet after the arbiter responds to the signal.

Abstract: The communication control device allows a plurality of data items to be transferred to and from external devices, such as a CPU and a memory, via an external bus having a different data bus width in DMA (direct memory access) transfer mode. DMA transfer is controlled by the DMA controller provided in the communication control device. The DMA controller produces a signal indicating that a plurality of data items are continual.