Abstract: A computer system consists of a plurality of nodes, each with an associated local host, coupled together with a plurality of point-to-point links. An isochronous data channel is established within the computer system between a first subset of the plurality of nodes. The isochronous data channel includes a linked list of buffers which are used as temporary storage locations for data transmitted on the isochronous data channel. Each node which is part of the isochronous data channel is configured as a sender or a receiver and data transmissions are commenced. The presence of isochronous data in the channel generates an interrupt which signals a central processing unit (CPU) that data is available. The data is transferred to an associated location within the linked list of buffers and the CPU then moves on to other tasks. In other embodiments, data is transferred using DMA techniques rather than interrupt driven events. Buffers can also be used to transmit isochronous data.

Abstract: A portable computer and corresponding docking station, where the portable computer may be inserted into or removed from the docking station without concern relating to the state of either the portable computer or of the docking station. The hot docking sequence is performed by establishing a direct connection to the primary PCI bus without the risk of any possible system damage, file damage, or data loss. This can be accomplished even while the portable computer system is powered on and is actively running. The present invention prevents glitches from occurring in pre-existing pins and adds four new pins to implement this novel hot docking sequence. Furthermore, hot undocking can be readily performed as well by basically reversing the docking sequence.

Abstract: A computer system includes a priority arbitration scheme that prevents "hogging" of a bus by a priority agent. The computer system comprises at least one agent, at least one priority agent, a system resource, and a bus coupling the agent, priority agent, and system resource to one another. An arbiter is coupled to the bus, agent, and priority agent to receive request signals from the agent and the priority agent and to grant control of the bus to one of the agent and priority agent for access to the system resource. The priority agent is granted control of the bus whenever the priority agent asserts a request signal, as soon as the bus becomes next available. The priority agent relinquishes control of the bus to the agent, for a predetermined portion of the bus bandwidth, when a request signal is asserted by the agent.

Abstract: The present invention supports computers or electronic devices that have a sleep, hibernation or low power mode. Because a device may appear to be off in low power mode, the present invention acts as an interlock to prevent or deter access to the device's electronics unless the power to the device has been disconnected or turned off.

Abstract: A method for reducing power consumption in a computer system is provided wherein the computer system includes a system bus interface connected by a signal line to a power supply and/or clock circuitry for the central processing unit, each having the capability to change the characteristic of its output responsive to the signal line for placing the central processing unit in a low-power consuming state. The system bus interface chip further including a storage location and counter for storing the type and quantity of interrupt assertions during the period of time when the central processing unit is in the low power consuming state.The system software determines the desired period of time to put the central processing unit into the low-power consuming state and does not return it to normal power consuming state until the time period has expired, a non interval clock interrupt is asserted, or another critical event occurs that needs immediate CPU attention.

Abstract: A control system for a communication apparatus has capability of coping with bus extension. The control system includes a control section and a plurality of controlled sections connected to the control section via a bus. Each controlled section accommodates at least one object to be controlled. The control section has a first interface for extension bus generation which includes a latch section and a bus transmission section. The controlled section has a second interface section for extension bus generation which includes a reception section, a judgment section, and a permission signal send-back section. The bus is formed by a bus which complies with a standard regarding mutual connection between apparatuses in a data communication system so as to send and receive pieces of information, each including a predetermined number of bits, and control signals. This makes it possible to suppress the hardware cost of channel sections and to efficiently perform highly functional monitoring and controlling.

Abstract: Arbitration circuitry in a computer system having a plurality of arbiters for arbitrating requests from bus masters on a PCI bus and an EISA bus. Each of the PCI and EISA buses have a plurality of masters. The PCI bus utilizes a modified LRU arbitration scheme, while the EISA bus utilizes a rotating priority scheme. The arbiter on the EISA bus includes a first level of arbitration and a second level of arbitration. The first level is assigned a plurality of requester types to determine the priority between the requestor types. Certain of the first level requestor types include a plurality of devices. If one of those certain requestor types wins priority on the first level arbitration cycle, a second level arbitration is performed to determine the priority between the plurality of devices.

Abstract: An interface apparatus or Nest (30) fits into a peripheral slot (24) connected to an IDE bus (60) of a host computer. IDE devices, such as magnetic tape drives and hard drives, are hot swapable in and out of Nest (30) while the IDE bus is active. The Nest isolates the IDE device from the active IDE bus until such time (e.g., initialization of the IDE device) as connection of the IDE device to the IDE bus will not corrupt the IDE bus, after which time the Nest connects the IDE device to the IDE bus while the IDE bus is active. A nest driver (230) is executed for computer systems (200) which tend to establish a permanent inventory of IDE devices upon system boot-up. The nest driver determines whether a Nest is connected to the host; determines whether an IDE device has been inserted in the Nest; and determines when the IDE device in the Nest has been initialized.

Abstract: A UART including a logic unit is disclosed, wherein the logic unit automatically enables or disables the UART receiver port whenever data is being processed by the UART for wireless transmission. More specifically, a logic unit is connected to a data store, to a transmit FIFO and to a UART processing unit as well as to an external CPU, wherein the logic unit analyzes the logic states of each of the signals from each of the specified connections to determine whether to enable or disable the receiver unit. An inventive method is also disclosed wherein the logic unit only enables the receiver when the data store is empty and the transmitter FIFO is empty and a receiver enable flag is set to true and a half duplex mode of operation has been specified by an external CPU. Otherwise, the logic enables the receiver only when a full duplex mode of operation has been specified and the receiver enable flag is set to a logic one.

Abstract: A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and/or keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare.

Abstract: A multiprocessor system having the capability of increasing the speed of a bus clock while retaining high reliability and fault tolerant performance as well as utilizing the current operating system resources. The multiprocessor system is made up of a plurality of processor modules connected together through a duplicated system bus. The duplicated system bus is divided into a plurality of segments, and these segments are coupled together by at least one bus extender mechanism. The multiprocessor system is also provided with first notification means which is provided between bus control mechanisms for controlling the states of physical buses and the bus extender mechanism, and the bus control mechanisms and the bus extender mechanism are mutually notified of the state of each mechanism through the first notification means.

Abstract: A hot-plug circuit for receiving a high-current load is disclosed. In accordance with a preferred embodiment of the present invention, the hot-plug circuit comprises a transistor, a capacitor, a resistor, and a control circuit module. The transistor is coupled between a power supply and an input that is adapted to receive the high-power adaptor card. The capacitor is coupled between a first terminal and a second terminal of the transistor. The resistor is coupled to the first terminal of the transistor. Finally, the control circuit module is for applying a first bias voltage to the second terminal of the transistor via the resistor in order to turn the transistor off during an absence of the high-current load, and for applying a second bias voltage to the second terminal of the transistor via the resistor in order to turn the transistor on under a linear conduction mode upon an initial contact of said high-current load to the input.

Abstract: The object is to control an interrupt request to be asserted to a host in all of a prereading mode, a postreading mode, and a both-reading mode. Until the count value of a counter becomes equal to the content of a delay register, the reset state of a flip-flop is held and an IRQ is not asserted to the host. When the read signal of a status register is input through an OR gate to a flip-flop for a period in which the count value of the counter becomes equal to the content of the delay register, the flip-flop is set and the Q output remains held in a logic high state, as the postreading mode or the both-reading mode. When the counter value of the counter becomes equal to the content of the delay register, the output of a comparator will go low and the flip-flop will be reset, so that the IRQ is asserted to the host by a CDR.

Abstract: A method and apparatus of assuring uniqueness of identification numbers of bus devices connected to a bus. Each bus device has a current identification number. At each of the bus devices, an identification number is received on a bus and the bus is contended for based on the received identification number. If more than one bus device is detected contending for the bus, the current identification number of one of the bus devices is changed. Each of the bus devices compares the received identification number to the current identification number of the bus device. A bus device provides a match indication, including driving a signal, if the comparison produces a match. Each bus device includes a collision detector for detecting if more than one bus device is driving the signal.

Abstract: A system for generating and maintaining lock files to inhibit conflicting requests for data files. A first process that accesses a data file generates a lock file to prohibit other processes from reading and/or writing that data file. Periodically the first process refreshes the lock file so that it shows a new modification time. A second process requesting access to the data file detect the lock file, stores the time of the attempted access, then waits a predetermined wait period and reads the lock file again. This is repeated, each time waiting for the wait period and again reading the lock file, until either (1) a predetermined time-out period passes without the first process refreshing the lock file, whereupon it is presumed that the process is defunct so the second process may access the data file; or (2) more than a maximum allowed access period of time has passed without the second process gaining access, i.e. the first process continues to refresh the lock file for greater than some predefined period.

Abstract: A method and apparatus for maximizing the performance of DMA transfers over a PCI.TM. bus are provided which includes a Per-Channel Retry count, Double Buffer Management, Wait Enable functionality, Back Up register functionality, Gather/Scatter mapping, a method for minimization of PIO writes, Read Semaphore functionality, a method for servicing of DMA transfers during FMU latency periods, Valid bit functionality, high and low water thresholds, and re-usable page tables.

Abstract: A resource allocation request and a resource release request of a PC card modem sent to a communication driver via a modem driver are hooked by a power saving driver. When the power saving driver detects that the resource allocation request is issued, the power saving driver first begins to supply power to the PC card modem by using a card service. Thereafter, the power saving driver transmits the hooked resource allocation request to the communication driver. Further, when the power saving driver detects that the resource release request is issued, the power saving driver transmits the hooked resource allocation request to the communication driver and stops the supply of power to the PC card modem by using the card service.

Abstract: A bus structure for interconnecting the modules of an industrial automation controller includes DATA lines and associated control lines that enable interface circuits on each module to transfer frames of data. The interface circuit includes a flow control circuit for managing resources within the receiving module, and thus controlling the flow of data over the backplane bus. As soon as a message begins to be received, the flow control circuit makes a determination as to the availability of resources within the module to successfully receive the data frame. If sufficient resources are not available, a busy indication is returned to the transmitting module, and the transmitting module then aborts the transmission.

Abstract: A method and apparatus for reducing power in a computer system having a counter and a phase generator. The method consists of receiving an input clock signal which has a plurality of clock cycles and receiving an enable signal. If the enable signal is active, then the counter performs a divide operation. In addition, a block signal is generated when the enable signal is active to hold the output signal in its present state. The block signal is removed if the divide operation is completed or if the enable signal becomes inactive. When the enable signal is not active, then the output signal generated is equal to and in phase with the input clock signal if the enable signal is not active.

Abstract: A computer system and method concurrently process transactions directed to computer devices coupled to a bus agent. The method transmits first and second transaction requests from one or more computer processors across a computer bus to the bus agent. The bus agent transmits the first transaction request to a first computer device coupled to the bus agent. In addition, the bus agent transmits the second transaction request to a second computer device before the bus agent has received a transaction response to the first transaction request from the first computer device, thereby concurrently processing the transaction requests. The bus agent includes plural device managers each uniquely associated with one of the computer devices. Each device manager employs a queue pointer into a transaction queue to track each transaction involving the computer device associated with the device manager.