Abstract: According to the present invention, an apparatus for arbitrating between several competing requests that has a number of components cooperate together is disclosed. A number of arbiter cells are provided. These arbiter cells contain a device for shifting a token value, a number of receptors for receiving request signals, and internal circuitry for selecting one of the request signals. The request signal selected by a given arbiter cell depends on the state of the request signals being received by the cell and the position of the cell's token. Also, one or more group arbiters are provided. These group arbiters contain a device for shifting a token value, a number of receptors for receiving request signals, and internal circuitry for selecting an arbiter cell. The arbiter cell eventually selected by a given group arbiter depends on the state of the request signals being received by the arbiter and the position of the arbiter's token.

Abstract: A spin buffer and associated method assure data integrity in shared resources in a computer system. Concurrent accesses to different semaphores by different devices are allowed. Lock and identification data within the semaphore is cached in the spin buffer so a device requesting access to a shared resource that corresponds to a semaphore that is represented in the spin buffer may determine whether any other device has ownership of the shared resource by accessing the data within the spin buffer, rather than reading from the semaphore. By caching semaphore lock information and allowing concurrent accesses to different semaphores by different devices, enhances system performance is achieved.

Abstract: A technique and system for isolating segments of a serial data bus for remote configuration of equipment in in-flight entertainment systems. The system allows the automatic initialization, or configuration, of multiple terminal units, attached to a serial data bus, without requiring physical access to the multiple units.

Abstract: A priority queue structure and algorithm for managing the structure which in most cases performs in constant time. In other words, most of the time the inventive algorithm performs its work in an amount of time that is independent on the number of priority classes or elements that exist in the queue. The queue itself consists of a linked list of elements ordered into subqueues corresponding to priority classes, with higher priority subqueues appearing earlier in the queue. An array of priority pointers contains an entry for each subqueue that points to the last element of each subqueue. Elements are removed for processing from the top of the queue. Removal takes constant time. Items are inserted into an appropriate subqueue by linking it at the end of its respective subqueue.

Abstract: A plurality of MOSFET switches, one per bus line, are used to solve the problem of interfacing between two incompatible devices via a single shared bus. The MOSFET switches used are simple, inexpensive, and very fast. The switches perform two primary functions: 1) isolation of two bus sections (possibly for loading reasons); and 2) translation of incompatible voltages transmitted over the bus.

Abstract: There is disclosed control circuitry for, and a method of controlling, multiple priority level interrupt request to a microprocessor in which output circuitry for outputting an interrupt identifier is operable only in response to an interrupt signal having a higher priority status than any currently executing interrupt process, and a microprocessor system and method of controlling a microprocessor system, incorporating such circuitry.

Abstract: A function of a switch apparatus is realized as an adapter. Signaling data which cannot be processed in the adapter, is output to a mainframe bus of a computer through an AAL controller, a RAM, and a bus controller. The computer processes the signaling data and sends it to a switch adapter through the mainframe bus. The signaling data is input to an 8.times.8 switch through the bus controller, the RAM, the AAL controller. Usual user information is switched by a PHY unit, a TC/ATM controller, an address converter, and the 8.times.8 switch. By connecting the switch adapter to the computer, it is possible for the computer to operate as a switch apparatus without damaging its function.

Abstract: A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.

Abstract: In the low power consumption data transfer bus of the present invention, the mode of division of a bus is associated with a specific layout on an actual LSI chip or an actual LSI-mounted board, and access frequency between functional blocks connected to the bus and therefore the effect of the bus division can be obtained to the maximum degree for the object of achievement of the low power consumption. Further, the operation speed of the bus (that is, data transfer speed) can be improved as compared to the case where the bus is not divided.

Abstract: A bridge coupling a primary bus to two secondary buses. The bridge contains three interfaces, one for the primary bus and the other two for the two secondary buses. Control circuitry is included within the bridge to support the execution of a transaction initiated by a bus master upstream of the bridge to a target downstream of the bridge. The bridge also supports the execution of a transaction initiated by a bus master coupled to either one of the secondary buses to a target upstream of the bridge.

Abstract: An object-oriented modular electronic component system comprises a plurality of self-contained operating modules, each having external mechanical and electromagnetic interconnecting devices. It includes a user module for performing a specific function, a database module for identifying the presence, location, and function of each of the operating modules of the system, a communications module for transmitting digital electromagnetic messages among the operating modules, a power supply module for providing electrical power to the operating modules, and a power bus device for delivering power from the power supply module to the operating modules. The communications module, the power supply module, the data base module, and the user module are all capable of being selectively operatively releasably connected, mechanically and electromagnetically. The modules are all electromagnetically disconnected in an inoperative mode and are electromagnetically connected in an operative mode.

Abstract: A method and apparatus for masking processor requests to improve bus efficiency includes a bus bridge having a detection logic for determining when a first processor on a first bus has been backed off the first bus a predetermined number of times. When the detection logic determines the first processor has been backed off the first bus the predetermined number of times, a timer is set to a first value, with the first value being sufficient to allow an agent on a second bus to access the first bus. A masking logic, coupled to the detection logic and the timer, is for masking requests from the first processor until the timer expires.

Abstract: A method or protocol for generating an Interrupt Signal for communication between a peripheral device and a host processor having either a level-sensitive or an edge-sensitive interrupt detector. After receiving an active interrupt request, and after confirming that the Chip Select signal is released, the interrupt signal is transitioned to an active level. After receiving an active Chip Select signal and multiple Clock pulses from the host as confirmation of receipt of the Interrupt Signal, the Interrupt Signal is transitioned to its inactive state. If the interrupt request is still pending, and when the Chip Select signal is released, then the Interrupt Signal is again made active. Maintaining the active level for the Interrupt Signal until the confirmation is returned from the host will activate level-sensitive detectors, while edge-sensitive detectors in the host will be activated by the multiple transitions ocurring if the host does not service the interrupt request in the peripheral.

Abstract: A support facility for installation of interprocessor unit cabling interconnecting the processor units of a multiple processor unit system in a first network, including a second system for directing the cabling interconnections of the first system and, in each processor unit of the first system, a device access controller connected through a second network to a second system, each device access controller including a memory for storing a unique identifier, and a network controller to interconnect to a network controller of at least one other processor unit. There is a selectably settable anchor bit indicator to indicate a processor unit selected as a first processor unit of the first network, a next connection indicator connected from the device access controller, and connected from the network controller, a transmit test indicator connected from the device access controller and a receive indicator connected from the device access controller.

Abstract: A multiprocessor system has a shared bus and a plurality of processor modules, wherein the shared bus includes an interrupt bus and each of the processor module contains an interrupt controller. The interrupt controller for performing an interrupt bus arbitration includes an interrupt bus arbiter. The interrupt bus arbiter has N number, e.g., 8 of arbitration cells, wherein each cell simultaneously receives a corresponding bit of the arbitration information, lower bits of the corresponding bit and corresponding lower bits of the wired-ORed interrupt bus data to generate an interrupt bus gain signal when the corresponding bits represent one logic state and the lower bits represent the other logic state; and a decision circuit connected to the arbitration cells for generating an interrupt bus gain decision signal when the interrupt bus gain signal is received.

Abstract: An interrupt mechanism handles an interrupt transaction between a source processor and a target processor on separate nodes in a multi-processor system. The nodes are connected to a network through node interface controls between the node and the network. The transaction begins by initiating the interrupt transaction at the source processor. The interrupt mechanism detects if the target processor is at a remote node on a system bus across the network, and if it is the mechanism sends an ignore signal to the source processor. Then the mechanism suspends the interrupt transaction at the source processor if it detects the target processor is at a remote node. The mechanism performs an ACK/NACK (acknowledge/non-acknowledge) operation at the target processor and returning an ACK signal or a NACK signal to the source processor across the network. This ACK/NACK signal wakes-up the source processor.

Abstract: A surround sound system for personal computer includes a control card and a PC surround decoder. The control card is a PC interface card for interfacing to the personal computer and draining the 5 VDC and .+-.12 VDC power from the personal computer as power source for both the control card and the PC surround decoder to operate. The PC surround decoder for processing the stereo source signal and generating left, center, right, surround and subwoofer signals. A connecting means electrically connects the PC surround decoder to the control card. The PC surround sound system is specified for incorporating with personal computer which enables the users to command the PC surround sound system with their computer keyboard or mouse and receive the full benefit of Dolby Surround encoded multimedia software and the like.

Abstract: A fibre channel disk drive operating system configures a plurality of disk drives into a fibre channel drive loop. The system also provides plurality of disk drive controllers, and a software controlled switching circuit electrically connecting the disk drive controllers to the disk drives which are arranged in the fibre channel drive loop in varying selected configurations. The switching circuit has a plurality of switch elements arranged for selectively electrically connecting each fibre channel drive loop to a selected controller. Each switch element in a first mode of operation passes electrical signals in a through direction and in a second mode of operation passes electrical signals in a second bypass direction. Thereby each fibre channel drive loop is electrically connected to a selected one of disk drive controllers prior to operation of the system.

Abstract: A microcontroller for use in battery charging and monitoring applications is disclosed. The microcontroller includes a microprocessor and various front-end analog circuitry such as a slope A/D converter and a multiplexer for allowing a plurality of analog input signals to be converted to corresponding digital counts indicative of signal level. The microcontroller also includes an I.sup.2 C interface for supporting a bi-directional two wire bus and data transmission protocol that is useful for serially communicating with other peripheral or microcontroller devices. By making use of the I.sup.2 C interface, the microcontroller can be programmed while in the end application circuit. Such a feature allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This allows the most recent firmware or a custom firmware to be programmed.

Abstract: A computer system having a central processing unit ("CPU"), a main memory divisible into allocable units, a secondary storage unit and an operating system for allocating the allocable units to tasks for use thereby is provided with a suspend circuit for creating an optimized compressed image of data in the main memory.