Abstract: A method and apparatus for improved indication of power-consumption status in a computer system is described. The computer system includes a light-emitting diode (LED) which produces an optical signal. The apparent intensity of the optical signal is controlled by a pulsed LED control signal having an adjustable duty cycle. By varying the duty cycle, the apparent intensity of the optical signal is varied. The rate at which the duty cycle is varied may be selected to produce an apparent intensity optical signal which varies continuously between a greatest and a least intensity. Also, the rate at which the duty cycle is varied may be selected from a plurality of rates, each corresponding with a one of a plurality of power-consumption states in which the computer system can operate.

Abstract: An applications programming interface implements and manages isochronous and asynchronous data transfer operations between an application and a bus structure. During an asyncronous transfer the API includes the ability to transfer any amount of data between one or more local data buffers within the application and a range of addresses over the bus structure using one or more asynchronous transactions. An automatic transaction generator may be used to automatically generate the transactions necessary to complete the data transfer. The API also includes the ability to transfer data between the application and another node on the bus structure isochronously over a dedicated channel. During an isochronous data transfer, a buffer management scheme is used to manage a linked list of data buffer descriptors. This linked descriptor list can form a circular list of buffers and include a forward pointer to the next buffer in the list and a backward pointer to the previous buffer in the list for each buffer.

Abstract: A computer system and method concurrently process transactions directed to computer devices coupled to a bus agent. The method transmits first and second transaction requests from one or more computer processors across a computer bus to the bus agent. The bus agent transmits the first transaction request to a first computer device coupled to the bus agent. In addition, the bus agent transmits the second transaction request to a second computer device before the bus agent has received a transaction response to the first transaction request from the first computer device, thereby concurrently processing the transaction requests. The bus agent includes plural device managers each uniquely associated with one of the computer devices. Each device manager employs a queue pointer into a transaction queue to track each transaction involving the computer device associated with the device. manager.

Abstract: An information processing apparatus for controlling a plurality of output devices includes a storage unit for storing respective characteristics of the plurality of output devices, a setting unit for setting a plurality of desired characteristics and priority thereamong, and a selection unit for selecting a desired output device from among the plurality of output devices based on the plurality of characteristics and the priority set by the setting unit and the characteristics stored in the storage unit.

Abstract: A system and process for power conservation in a portable computer system. When the application or hardware in use allows for reduced video performance, the refresh rate of the video graphics controller is reduced to a level which allows practical use of the display but consumes much less power than a normal mode.

Abstract: A computer system includes a plurality of processor modules coupled to a system bus with each of said processor modules including a processor interfaced to the system bus. The processor module has a backup cache memory and tag store. An index bus is coupled between the processor and the backup cache and backup cache tag store with said bus carrying only an index portion of a memory address to said backup cache and said tag store. A duplicate tag store is coupled to an interface with the duplicate tag memory including means for storing duplicate tag addresses and duplicate tag valid, shared and dirty bits. The duplicate tag store and the separate index bus provide higher performance from the processor by minimizing external interrupts to the processor to check on cache status and also allows other processors access to the processor's duplicate tag while the processor is processing other transactions.

Abstract: A device for controlling data transmission between a docking station and a portable computer includes signal control circuitry connected to the docking station for selectively enabling and disabling data transmission between the docking station and the portable computer to enable and disable expanded operating functions of the portable computer, respectively. The signal control circuitry enables and disables the data transmission between the docking station and the portable computer in dependence upon a first signal indicating a power supply state of the docking station, a second signal indicating a power supply state of the portable computer, and a third signal indicating a connection state between the docking station and the portable computer.

Abstract: A buffer flush controller, of a peripheral component interconnect-peripheral component interconnect bridge (PPB), includes a first compounding circuit, a first state machine, a second state machine, and a second compounding circuit. The buffer flush controller can maintain data consistency by efficiently controlling a flush operation of a data buffer of a peripheral component interconnect bridge, and the buffer flush controller can ensure a normal system operation without deadlock.

Abstract: A computer system and method concurrently process transactions directed to computer devices coupled to a bus agent. The method transmits first and second transaction requests from one or more computer processors across a computer bus to the bus agent. The bus agent transmits the first transaction request to a first computer device coupled to the bus agent. In addition, the bus agent transmits the second transaction request to a second computer device before the bus agent has received a transaction response to the first transaction request from the first computer device, thereby concurrently processing the transaction requests. The bus agent includes plural device managers each uniquely associated with one of the computer devices. Each device manager employs a queue pointer into a transaction queue to track each transaction involving the computer device associated with the device. manager.

Abstract: A switcher for selectively routing a plurality of input signals to a plurality of output signal ports. The switcher includes a motherboard disposed in a housing, and a switch card for routing ones of the input signals to an output card, wherein the output card functions to amplify signals received from the switch card. The output card and the switch card are also disposed in the housing, and are electronically coupled to each other and to the motherboard by a signal bus on the motherboard. A controller card is provided for controlling the routing of the input signals to the output signal ports. The controller card, the output card, and the switch card are electronically coupled to each other and to the motherboard by a control bus on the motherboard.

Abstract: A continuous data server includes a storage unit connected to a buffer memory which is in turn connected to a plurality of communication control units which transfer data of the buffer memory to a network. The right to use a bus interconnecting the buffer memory and communication control units is deterministically assigned by a micro-scheduler in accordance with a program stored in a micro-schedule table. The micro-scheduler allocates the right to use the bus in accordance with a predetermined schedule, rather than by arbitration.

Abstract: An integrated power supply device and a power supplying method for controlling power supply to a computer system having a main computer body and a monitor.

Abstract: A method and apparatus for maximizing the performance of DMA transfers over a PCI.TM. bus are provided which includes a Per-Channel Retry count, Double Buffer Management, Wait Enable functionality, Back Up register functionality, Gather/Scatter mapping, a method for minimization of PIO writes, Read Semaphore functionality, a method for servicing of DMA transfers during FMU latency periods, Valid bit functionality, high and low water thresholds, and re-usable page tables.

Abstract: This invention presents the serial arbitration method and system for rapidly and accurately identifying a station with the highest priority when a plurality of stations with different transmission rates are simultaneously requesting the use of a bus in a multi-point communication network where a plurality of communication stations share a common serial bus.This invention intends to improve the bus throughput by not only avoiding the collision of signals in a common serial bus, but also removing the possibility of arbitration failures when a plurality of contending stations have different transmission rates.For this purpose, a plurality of contending stations transmit modulated unique identity address serially in a form of self-clocking pulse on the OR-type single channel bus when the arbitration start signal is detected in multi-point networks.

Abstract: A computer bus includes a set of computer bus input nodes to receive a set of computer bus input signals generated by system cards attached to the computer bus. The computer bus input signals are processed by a set of bus bit processors. Each of the bus bit processors includes a digital gate logic circuit to perform a logical OR operation on a subset of the set of computer bus input signals. The subset of computer bus input signals corresponds to the signals carried by a single line of a traditional computer bus. Each bus bit processor generates a bus bit processor output signal. The set of bus bit processors thereby form a set of bus bit processor output signals. The bus bit processor output signals are applied to computer bus output nodes for processing by the system cards in a conventional manner. Thus, the digital gate logic circuits of the bus bit processors execute the function performed by traditional hardwired computer bus structures.

Abstract: In a networked computer system that includes an omnibus system coupled to a plurality of workstation/computer subsystems, an optimal global reordering of transactions seeking Address Bus access is provided. Access requests are asserted by devices associated with circuit cards, each such card including an address controller, memory, and a coherent input queue. Transactions occurring on the omnibus are loaded into the associated address controller coherent input queue. A global network interface is coupled to the omnibus system and may assert an IGNORE signal, amd includes a table storing all cache lines in the distributed memory system. A transaction seeking to access an address holding invalid data or a remote address is detected by the global network interface, which asserts the IGNORE signal, thus blocking the transaction from loading into the coherent input queue. At a later time when the subject address retains valid data, the interface reissues an identical transaction on the bus.

Abstract: An off-hook state of a telephone associated with a computer is used in order to disable the power management unit of the computer to prevent premature power shutdown while the telephone is being used. A power-managed computer system includes a bus system, and a central processing unit coupled to the bus system. The central processing unit has a normal power mode and a power saving mode. A telephony interface coupled to the bus system has a port for coupling to a telephone system network. A power management unit is also coupled to the bus system and is responsive to bus system activity and to indicia of telephony interface activity. The power management unit causes the central processing unit to be in a power saving mode when both bus system activity and telephony interface activity are less than a predetermined level of activity.

Abstract: A power control system for a microprocessor, having multiple parallel operated execution units, functions to disable some of the execution units to conserve power and/or reduce heat. The execution units are disabled by preventing the application of clock pulses to these execution units. This operation is effected by a power control unit which enables and disables gates coupled between a source of clock signals and the execution units.

Abstract: A method and apparatus for improved indication of power-consumption status in a computer system is described. The computer system includes a light-emitting diode (LED) which produces an optical signal. The apparent intensity of the optical signal is controlled by a pulsed LED control signal having an adjustable duty cycle. By varying the duty cycle, the apparent intensity of the optical signal is varied. The rate at which the duty cycle is varied may be selected to produce an apparent intensity optical signal which varies continuously between a greatest and a least intensity. Also, the rate at which the duty cycle is varied may be selected from a plurality of rates, each corresponding with a one of a plurality of power-consumption states in which the computer system can operate.

Abstract: A method and apparatus for controlling access to a bus. A target having a period of unavailability is identified. A master device requesting access to the bus to initiate a data transfer between the master device and the target device also is identified. The master device is denied access to the bus for a delay period in response to the master device attempting to retry a data transfer with the target device, wherein the delay period is a time period after which the target device becomes available for additional transfers, wherein the bus is available to other master devices during the delay period.