Abstract: In a computer system having a plurality of electronic subsystems therein adapted to receive main electrical power from an interruptible main power supply, ones of the electronic subsystems being designated as critical to retention of user data in the computer system in an event of interruption of the electrical power from the main power supply, a backup power subsystem and method for controllably delivering backup electrical power to the ones of the electronic subsystems. The subsystem comprises: (1) a central electrical power storage cell having a particular capacity and adapted to be maintained in a constantly charged state, (2) a backup electrical power bus coupled to the central electrical power storage cell and adapted to be selectively coupled to selected ones of the electronic subsystems and (3) a backup power management controller adapted to couple the backup electrical power bus to the selected ones of the electronic subsystems.

Abstract: A bus interface unit disposed for incorporation within a microprocessor system having a local microprocessor bus, a memory unit, and a system bus coupled to the memory unit is disclosed herein. The bus interface unit includes a bus control unit having an address latch for latching N-bit memory addresses impressed upon the local microprocessor bus by the microprocessor. Each of the N-bit memory addresses identifies one or more M-bit memory locations within the memory unit. The bus interface unit further includes a multiplexing interface for transferring data associated with the M-bit memory locations between the system bus and the local microprocessor bus during microprocessor memory access cycles. A programmable wait state generator serves to control the duration of the microprocessor memory access cycles in order to accommodate address and data transfer between the system bus and the local microprocessor bus during both memory read and write access cycles.

Abstract: An audio power management system for a computer to eliminate noise signals associated with the power-down and power-up operations of the computer during power management operations. The audio power management system asserts a speaker mute signal before power is removed from the amplifier to reduce transient conditions. During power up, the speaker mute signal is applied to the amplifier for a period after power is applied to the amplifier. This control is done from a single digital output.

Abstract: A multiple frequency zoned disk storage device in which data is read from and/or written to the disk at two or more discrete disk velocities is disclosed. The disk storage device includes a low power mode where information is read/written from/to the disk while the disk velocity is reduced to conserve power. The allocation track locations into zones on the drive reduces the number of zone bit frequencies the storage device must handle.

Abstract: A multiple-transaction peripheral bus is provided with multiplexed address and data lines which is particularly adapted for portable applications. The multiple-transaction peripheral bus accommodates compatibility with existing hardware designs for a higher performance bus system with minimal conversion logic. A bus conversion bridge provides an interface between a 32-bit Peripheral Component Interconnect (PCI) bus and a 16-bit transaction Address/Data (A/D) which is associated with half the number of multiplexed address/data lines in comparison with the 32-bit PCI bus. The PCI bus accommodates data transfers between master and slave devices associated therewith, as does the narrower multiple-transaction A/D bus. The bus conversion bridge accommodates data transfers between the two buses, allowing a master device on one bus to communicate with a slave device on the other bus.

Abstract: An adapter or add-in card for using in a peripheral component interconnect (PCI) computer includes a universal module which couples the card to the PCI bus. The module includes a set of selectively programmable configuration registers which are loaded by a microprocessor on the adapter. A circuit arrangement on the module issues a command which inhibits the PCI processor from accessing the configuration registers until fully loaded.