Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The first mold compound resides over the active layer without silicon crystal, which has no germanium content, in between. The multilayer redistribution structure includes redistribution interconnections and a number of bump structures that are at bottom of the multilayer redistribution structure and electrically coupled to the mold device die via the redistribution interconnections.

Abstract: The present invention provides a display panel and manufacturing method thereof, the method including following steps: providing a driving backplane and a light-emitting substrate, and bonding the driving backplane and the light-emitting substrate; patterning the light-emitting substrate to form a pixel array; forming a thin film packaging layer on an outside of the pixel array, the thin film packaging layer completely covering the pixel array; forming quantum dots on top of the thin film packaging layer to form a multi-color display; forming a reflective array between two adjacent quantum dots to avoid optical crosstalk between the pixel arrays. The display panel and the method of the present invention break through the physical limit of the high PPI, high-precision metal mask, which can realize the display of 2000 and higher PPI, and can prevent the optical crosstalk between the pixel arrays.

Abstract: A display panel includes a pad line disposed on a rear surface of a base layer and a connection line disposed on a front surface of the base layer. The pad line and the connection line are connected in an area overlapping a pad hole defined to pass through the base layer, and the pad line is connected to a driving unit on the rear surface of the base layer.

Abstract: A packaged device (110) includes a substrate (114) and one or more contacts (118) disposed on a side of the substrate (114). Structures of the packaged device (110) define at least in part a recess region (120) that extends from the side of the substrate (114) and through the substrate (114), where one or more contacts (124) of a second hardware interface are disposed in the recess region (120). The one or more contacts (118) of the first hardware interface enable connection of the packaged device (110) to a printed circuit board. The one or more contacts (124) of the second hardware interface enable connection between one or more IC dies of the packaged device (110) and another IC die (150) that is a component of the packaged device (110) or of a different packaged device.

Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Abstract: A bonding head for a die bonding apparatus and a die bonding apparatus including the bonding head, the bonding head including a head body; a thermal pressurizer mounted on a lower surface of the head body, the thermal pressurizer being configured to hold and heat at least one die and including a heater having a first heating surface that faces a held surface of the die; and a thermal compensator at an outer region of the die, the thermal compensator extending downwardly from the lower surface of the head body and including at least one thermal compensating block having a second heating surface that emits heat from a heating source therein and that faces a side surface of the die held on the thermal pressurizer.

Abstract: Semiconductor devices include a semiconductor layer structure comprising a drift region that includes a wide band-gap semiconductor material. A shielding pattern is provided in an upper portion of the drift region in an active region of the device and a termination structure is provided in the upper portion of the drift region in a termination region of the device. A gate trench extends into an upper surface of the semiconductor layer structure. The semiconductor layer structure includes a semiconductor layer that extends above and at least partially covers the termination structure.

Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

Abstract: A method includes providing an active pattern and gate metal patterns, and inorganic insulation layers respectively therebetween in a pixel area and each extending to a bending area, providing a first photoresist pattern defining a first opening in the bending area, providing by using the first photoresist pattern, at least one of the inorganic layers in the bending area which is etched, providing a remaining photoresist pattern defining a first remaining opening corresponding to the first opening and a second opening corresponding to the active pattern, and providing by using the remaining photoresist pattern, both a contact hole corresponding to the second opening and exposing the portion of the active pattern to outside the remaining photoresist pattern, and a portion of the base substrate corresponding to the first remaining opening and exposed to outside the remaining photoresist pattern.

Abstract: This organic EL device (100) has a substrate (1), a drive circuit layer (2), a first inorganic protective layer (2Pa), an organic planarizing layer (2Pb), an organic EL element layer (3), a second inorganic protective layer (2Pa2), and a TFE structure (10). The TFE structure has a first inorganic barrier layer (12), an organic barrier layer (14), and a second inorganic barrier layer (16). When viewed from a normal line of the substrate, the organic planarizing layer is formed within a region where the first inorganic protective layer is formed, while an organic EL element is disposed within a region where the organic planarizing layer is formed. The TFE structure has an exterior edge which intersects with a lead-out line (32) and which is situated between an exterior edge of the organic planarizing layer and an exterior edge of the first inorganic protective layer.

Abstract: The present disclosure provides an organic light-emitting display panel, a method of manufacturing the organic light-emitting display panel, and a display apparatus. The organic light-emitting display panel includes: a substrate having an opening passing through the substrate; a pixel array disposed on the substrate and including a plurality of pixels; an isolation part disposed between the plurality of pixels and the opening and surrounding the opening, wherein the isolation part includes: a first layer disposed on the substrate, wherein the first layer includes a first portion and a second portion which are sequentially stacked in a direction away from the substrate, and an orthogonal projection of the first portion on the substrate falls within an orthogonal projection of the second portion on the substrate; and a second layer disposed on a surface of the first layer away from the substrate.

Abstract: A display apparatus includes a substrate including a first display area and a second display area. The second display area includes a transmission area, a plurality of first opposite electrodes and a plurality of second opposite electrodes each corresponding to the first display area, and a plurality of third opposite electrodes and a plurality of fourth opposite electrodes each corresponding to the second display area and surrounding at least a portion of the transmission area. A shape of each of the plurality of first opposite electrodes is the same as that of each of the plurality of third opposite electrodes.

Abstract: Provided are a display panel including: a first component, a second component, and a bending component connecting the first component and the second component; wherein, the first component has a display surface, and the bending component has a via passing through the bending component in a direction perpendicular to the display surface. A display device is also provided.

Abstract: A semiconductor device includes a first device fin and a second device fin that are each located in a first region of the semiconductor device. The first region has a first pattern density. A first dummy fin is located in the first region. The first dummy fin is disposed between the first device fin and the second device fin. The first dummy fin has a first height. A third device fin and a fourth device fin are each located in a second region of the semiconductor device. The second region has a second pattern density that is greater the first pattern density. A second dummy fin is located in the second region. The second dummy fin is disposed between the third device fin and the fourth device fin. The second dummy fin has a second height that is greater than the first height.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to diode triggered Silicon controlled rectifiers and methods of manufacture. The structure includes a diode string comprising a first type of diodes and a second type of diode in bulk technology in series with the diode string of the first type of diodes.

Abstract: An apparatus including a transistor device disposed on a surface of a circuit substrate, the device including a body including opposing sidewalls defining a width dimension and a channel material including indium, the channel material including a profile at a base thereof that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body including opposing sidewalls and including a buffer material and a channel material on the buffer material, the channel material including indium and the buffer material includes a facet that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls; and forming a gate stack on the channel material.

Abstract: Provided are a display device and a method of repairing the display device, wherein a defective pixel is repaired using a bankless structure that includes a repair pattern.

Abstract: A display device includes a substrate including a display area to display an image and a non-display area provided on at least one side of the display area, a plurality of pixels disposed on the substrate and provided in an area corresponding to the display area, a first insulating layer having an opening in a first area of the non-display area, a second insulating layer provided in the first area, first lines provided on the substrate and connected to the plurality of pixels, and second lines provided on the first and second insulating layers, and connected to the first lines. An area in which the first lines overlap with the second lines is spaced apart from an edge of the second insulating layer when viewed in a plan view.