Abstract: As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of high manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

Abstract: A display device including a lower substrate having a display region including a plurality of pixel regions, and a peripheral region surrounding the display region; a plurality of pixel structures in the plurality of pixel regions on the lower substrate; an upper substrate on the plurality of pixel structures; a seal between the lower substrate and the upper substrate in the peripheral region; and a power supply voltage wiring between the seal and the lower substrate in the peripheral region, wherein the power supply voltage wiring partially overlaps the seal, and the power supply voltage wiring includes a plurality of first openings in a portion thereof that protrudes inwardly from the seal in a first direction extending from the peripheral region into the display region.

Abstract: A display device includes a first subpixel including a light-emitting layer of a first color, a second subpixel adjacent to the first subpixel in a row direction or a column direction, the second subpixel including a light-emitting layer of a second color, and a third subpixel adjacent to the first subpixel and the second subpixel in a diagonal direction, the third subpixel including a light-emitting layer of a third color, wherein the first subpixel to the third subpixel include light-emitting regions that are geometrically similar to one another, the light-emitting regions of two of the first subpixel to the third subpixel are in the same size, and a light-emitting region of remaining one of the first subpixel to the third subpixel is larger than the light-emitting regions of the two of the first subpixel to the third subpixel.

Abstract: A wiring line is provided on a TFT layer, in which the wiring line is formed in the same layer and formed of the same material as those of a reflection electrode. The reflection electrode includes a plurality of metallic conductive layers made up of a low resistance metallic material, an oxide-based lower transparent conductive layer provided on a lower surface side of a lowermost metallic conductive layer constituting a lowermost layer, an oxide-based upper transparent conductive layer having light reflectivity and provided on an upper surface side of an uppermost metallic conductive layer constituting an uppermost layer, and an oxide-based intermediate transparent conductive layer provided between the plurality of metallic conductive layers.

Abstract: A number of new solutions for enhancing the extraction of waveguided mode and suppressing surface plasmon polariton mode in OLEDs are disclosed.

Abstract: An array substrate, an electroluminescent display panel, and a display device are disclosed. The array substrate includes: a base substrate, and a first signal line, an insulating layer and a second signal line provided sequentially on the base substrate in a direction perpendicular to the base substrate; wherein the first signal line has a first portion and a second portion, the first portion has a resistance higher than a resistance of the second portion, and at least a part of the first portion is overlapped with the second signal line, and the second portion is non-overlapped with the second signal line.

Abstract: An organic light emitting diode display device including a substrate having a display region, a peripheral region around the display region, and a pad region located on one side of the peripheral region, a sub-pixel structure in the display region on the substrate, a plurality of fan-out wires on the substrate and located in the peripheral region, each one of the fan-out wires including a first diagonal portion, a first straight portion, and a second diagonal portion, a first sub-power supply wire on the fan-out wires and located in the peripheral region, and a first planarization layer on the first sub-power supply wire and having an opening configured to expose the first sub-power supply wire on a portion at which the first straight portion of each of the fan-out wires is located.

Abstract: An optoelectronic semiconductor chip including a semiconductor layer sequence containing a phosphide compound semiconductor material, wherein the semiconductor layer sequence includes a p-type semiconductor region, an n-type semiconductor region and an active layer disposed between the p-type semiconductor region and the n-type semiconductor region, a current spreading layer including a transparent conductive oxide adjoining the p-type semiconductor region, and a metallic p-connection layer at least regionally adjoining the current spreading layer, wherein the p-type semiconductor region includes a p-contact layer adjoining the current spreading layer, the p-contact layer contains GaP doped with C, a C dopant concentration in the p-contact layer is at least 5*1019 cm?3, and the p-contact layer is less than 100 nm thick.

Abstract: A method of manufacturing a light-emitting display apparatus and a light-emitting display apparatus are provided. The method includes forming a first photosensitive layer on a conductive material layer, forming a pixel electrode by etching the conductive material layer by using the first photosensitive layer as a mask, ashing the first photosensitive layer disposed on the pixel electrode, forming a pixel defining layer that covers an edge portion of the pixel electrode and includes a first opening overlapping the ashed first photosensitive layer, removing the ashed first photosensitive layer disposed in the first opening, forming an intermediate layer including a functional layer and an emission layer on the pixel defining layer, and forming an opposite electrode on the intermediate layer.

Abstract: A method of forming an IC structure includes providing a metal gate structure, a spacer adjacent the metal gate structure and a contact to each of a pair of source/drain regions adjacent sides of the spacer. The spacer includes a first dielectric having a first dielectric constant. The metal gate structure is recessed, and the spacer is recessed to have an upper surface of the first dielectric below an upper surface of the metal gate structure, leaving a lower spacer portion. An upper spacer portion of a second dielectric having a dielectric constant lower than the first dielectric is formed over the lower spacer portion. A gate cap is formed over the metal gate structure and the upper spacer portion. The second dielectric can include, for example, an oxide or a gas. The method may reduce effective capacitance and gate height loss, and improve gate-to-contact short margin.

Abstract: Embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. The device includes a plurality of sub-pixels, each sub-pixel of the plurality of sub-pixels defined by adjacent pixel-defining layer (PDL) structures with inorganic overhang structures disposed on the PDL structures, each sub-pixel having an anode, organic light-emitting diode (OLED) material disposed on the anode, and a cathode disposed on the OLED material. The device is made by a process including the steps of: depositing the OLED material and the cathode by evaporation deposition, and depositing an encapsulation layer disposed over the cathode.

Abstract: Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.

Abstract: Embodiments relate to nanoporous copper interconnects on a first body for electrically connecting to a second body. To fabricate the nanoporous copper interconnect, a zinc-copper alloy is deposited on recesses on the surface of the first body, and then the zinc is removed from the zinc-copper alloy to obtain nanoporous copper. The first body and the second body can be attached using bonding between oxide surfaces of the two bodies or be provided with underfill between the two bodies. The nanoporous copper electrically connects to an active layer or electrical components of the first body and the second bodies. Using nanoporous copper as interconnects is advantageous, among other reasons, because it can be formed at a low temperature, it is compatible with a standard complementary metal-oxide-semiconductor (CMOS) process, it provides good electrical conductivity, and it is less likely to cause issues due to migration of material.

Abstract: A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

Abstract: A power-module substrate and a heat sink made of an aluminum-impregnated silicon carbide formed by impregnating aluminum in a porous body made of silicon carbide; where yield strength of a circuit layer is ?1 (MPa), a thickness of the circuit layer is t1 (mm), a bonding area of the circuit layer and a ceramic board is A1 (mm2), yield strength of a metal layer is ?2 (MPa), a thickness of the metal layer is t2 (mm), a bonding area of the metal layer and the ceramic board is A2 (mm2); the thickness t1 is formed to be between 0.1 mm and 3.0 mm (inclusive); the thickness t2 is formed to be between 0.15 mm and 5.0 mm (inclusive); the thickness t2 is formed larger than the thickness t1; and a ratio {(?2×t2×A2)/(?1×t1×A1)} is in a range between 1.5 and 15 (inclusive).

Abstract: An organic light emitting display device includes a plurality of sub pixels including a plurality of red sub pixels, a plurality of green sub pixels, and a plurality of blue sub pixels, wherein each sub pixel of the plurality of sub pixels includes an emission region and a non-emission region surrounding the emission region, wherein each sub pixel of the plurality of sub pixels has the same size, wherein areas of emission regions of green sub pixels are the same as or larger than an area of an emission region of at least one red sub pixels and blue sub pixels, and wherein the emission region of green sub pixels extends into a portion of the non-emission region of the red sub pixels or a portion of the non-emission region of the blue sub pixels.

Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.

Abstract: A semiconductor device includes a first substrate; a dielectric layer disposed over the first substrate and a conductive layer disposed in the dielectric layer; a second substrate bonded to the dielectric layer, wherein the second substrate has a first surface facing the first substrate and a second surface opposite to the first substrate; a connecting structure penetrating the second substrate and a portion of the dielectric layer and electrically coupled to the conductive layer; a vent hole penetrating the second substrate from the second surface to the first surface; a first buffer layer between the connecting structure and the dielectric layer and between the connecting structure and the second substrate; and a second buffer layer covering sidewalls of the vent hole and exposed through the first surface of the second substrate. The first buffer layer and the second buffer layer include a same material and a same thickness.

Abstract: An organic light emitting diode display includes: a substrate; a first electrode on the substrate; a second electrode opposed to the first electrode; a first light emitting unit and a second light emitting unit between the first electrode and the second electrode; and a charge generation layer between the first light emitting unit and the second light emitting unit. The first light emitting unit includes a blue fluorescent light emitting layer. The second light emitting unit includes a blue light emitting layer and a yellow light emitting layer.

Abstract: The method of manufacturing an integrated circuit includes obtaining a silicon carbide substrate of a first conductivity type having an epitaxial layer of a second conductivity type thereon. A dopant is implanted in the epitaxial layer to form a first region of the first conductivity type that extends the full depth of the epitaxial layer. A first transistor is formed in the first region and a second transistor is formed in the epitaxial layer.