Abstract: A semiconductor package includes: a connection member having a first surface and a second surface opposing each other in a stacking direction of the semiconductor package and including an insulating member and a redistribution layer formed on the insulating member and having a redistribution via; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; a passivation layer disposed on the second surface of the connection member; UBM pads disposed on the passivation layer and overlapping the redistribution vias in the stacking direction; and UBM vias connecting the UBM pads to the redistribution layer through the passivation layer, not overlapping the redistribution vias with respect to the stacking direction, and having a non-circular cross section.

Abstract: A display device comprises: a base layer, islands and bridges, the islands and the bridges disposed on the base layer, the bridges connecting the islands to each other, first wirings disposed on the bridges, pixels disposed on the islands, the first wirings disposed on the bridges, pixels disposed on the islands, the first wirings being connected to the pixels; an inorganic insulating layer disposed on the base layer, the inorganic insulating layer includes an opening exposing the base layer of a bridge region having the bridges; second wirings disposed in the opening; and a first organic insulating layer disposed between the first wirings and the second wirings, where the first wirings and the second wirings are connected to each other through first contact holes formed in the first organic insulating layer.

Abstract: A semiconductor device includes a fin projecting upwardly from a substrate; a gate stack engaging the fin; a gate spacer on a sidewall of the gate stack and in contact with the gate stack; and a dielectric layer on the sidewall of the gate stack and in contact with the gate stack, the dielectric layer being vertically between the fin and the gate spacer, wherein the dielectric layer has a thickness small than the gate spacer.

Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The first mold compound resides over the active layer without silicon crystal, which has no germanium content, in between. The multilayer redistribution structure includes redistribution interconnections and a number of bump structures that are at bottom of the multilayer redistribution structure and electrically coupled to the mold device die via the redistribution interconnections.

Abstract: A semiconductor device includes a core insulating layer extending in a first direction, an etch stop layer disposed on the core insulating layer, a channel layer extending along a sidewall of the core insulating layer and a sidewall of the etch stop layer, conductive patterns each surrounding the channel layer and stacked to be spaced apart from each other in the first direction, and an impurity region formed in an upper end of the channel layer.

Abstract: A display device includes: a substrate having a display area and a non-display area; a lower connection line disposed in the non-display area; a bank layer disposed on the lower connection line and having an undercut structure at an edge of a lower end portion thereof; a bank etch layer disposed between the lower connection line and the bank layer and having an edge inside the edge of the lower end portion of the bank layer; and a second driving electrode disposed on the bank layer and electrically connected to the lower connection line at least once, wherein a plurality of bank holes are formed in the bank layer.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes pixel circuits arranged in a matrix, and a blocking unit. Each pixel circuit includes: a driving transistor; a first switch transistor; a second switch transistor; and a third switch transistor. The blocking unit is configured to receive a fixed potential signal, and at least a partial area of the blocking unit is located between a first semiconductor connection portion and a second semiconductor connection portion, the first semiconductor connection portion is connected between a second electrode of the first switch transistor and a gate electrode of the driving transistor, and the second semiconductor connection portion is electrically connected between a first electrode of the second switch transistor and a data line.

Abstract: A display apparatus is discussed, which comprises a substrate including a display area and a non-display area, an inorganic layer provided on the substrate, an organic layer provided on the inorganic layer, a light emitting diode provided in the display area of the substrate and including a first electrode, a light emitting layer and a second electrode, and a ground line provided on the organic layer and provided in at least a portion of the non-display area, wherein the ground line and the second electrode are electrically connected with each other, and the ground line includes at least one concave portion and at least one convex portion, which are arranged to adjoin each other.

Abstract: A semiconductor device includes: a metal thin film disposed on a semiconductor substrate; and first and second contact structures disposed on the metal thin film, wherein the first and second contact structures are laterally spaced from each other by a dummy layer that comprises at least one polishing resistance material.

Abstract: The present disclosure provides an OLED display panel and a method for detecting the OLED display panel, and a display device. The OLED display panel includes a base substrate including a display area and a non-display area surrounding the display area and having a first region adjacent to the display area. The display area includes a drive signal line and a power supply voltage signal line both extending from the display area to the first region. The drive signal line includes, in the first region, a first section of wiring at an anode layer, the power supply voltage signal line includes, in the first region, a second section of wiring at a gate metal layer, and parts of the drive signal line and the power supply voltage signal line in the display area are located at a source-drain metal layer.

Abstract: A device is disclosed. In an embodiment the device includes an anode, an organic active layer above the anode, an organic layer sequence above the organic active layer, a metallic layer above the organic layer sequence and a cathode above the metallic layer, wherein the metallic layer includes Yb.

Abstract: A display apparatus includes a substrate including at least one hole disposed in a hole area of the substrate, a thin film transistor disposed on the substrate, a light-emitting component disposed on the substrate and electrically connected to the thin film transistor, an insulating layer disposed on the substrate, a thin film encapsulation layer disposed on the substrate, and a laser blocking layer. The substrate includes a display area and a non-display area that is disposed between the display area and the hole area. The laser blocking layer is disposed on the insulating layer in the non-display area.

Abstract: The method of manufacturing an integrated circuit includes obtaining a silicon carbide substrate of a first conductivity type having an epitaxial layer of a second conductivity type thereon. A dopant is implanted in the epitaxial layer to form a first region of the first conductivity type that extends the full depth of the epitaxial layer. A first transistor is formed in the first region and a second transistor is formed in the epitaxial layer.

Abstract: A bonding head for a die bonding apparatus and a die bonding apparatus including the bonding head, the bonding head including a head body; a thermal pressurizer mounted on a lower surface of the head body, the thermal pressurizer being configured to hold and heat at least one die and including a heater having a first heating surface that faces a held surface of the die; and a thermal compensator at an outer region of the die, the thermal compensator extending downwardly from the lower surface of the head body and including at least one thermal compensating block having a second heating surface that emits heat from a heating source therein and that faces a side surface of the die held on the thermal pressurizer.

Abstract: Power MOS device, in which a power MOS transistor has a drain terminal that is coupled to a power supply node, a gate terminal that is coupled to a drive node and a source terminal that is coupled to a load node. A detection MOS transistor has a drain terminal that is coupled to a detection node, a gate terminal that is coupled to the drive node and a source terminal that is coupled to the load node. A detection resistor has a first terminal coupled to the power supply node and a second terminal coupled to the detection node.

Abstract: An organic light emitting device includes a first substrate including a display area and a non-display area, and a dummy metal layer disposed on the first substrate in the non-display area. The dummy metal layer includes a first dummy metal layer and a second dummy metal layer that overlap each other. The organic light emitting device further includes an insulating layer disposed between the first dummy metal layer and the second dummy metal layer in a cross-sectional view, a second substrate covering the first substrate, and a sealant disposed between the first substrate and the second substrate and overlapping the dummy metal layer. The first dummy metal layer is electrically connected to the second dummy metal layer, and the sealant contacts the second dummy metal layer.

Abstract: A display substrate, a manufacturing method therefor and a pixel driving circuit, the display substrate includes: a base substrate; a first conductive layer, which includes a first signal line, a second signal line, and an additional pad layer, on the base substrate; a pixel defining layer on the first conductive layer and having an opening; and an electroluminescent material layer in the opening and including a first end portion and a second end portion, an orthographic projection of the first end portion on the base substrate falls within that of the first signal line, an orthographic projection of the second end portion on the base substrate falls within that of the additional pad layer, and the orthographic projections of the first end portion and the second end portion are respectively located on both sides of an orthographic projection of the second signal line on the base substrate.

Abstract: A display device includes pixels connected to scan lines and data lines intersecting the scan lines, wherein each of the pixels includes a light-emitting element, a driving transistor to control a driving current supplied to the light-emitting element according to a data voltage applied from the data lines, and a switching transistor to apply the data voltage of the data line to the driving transistor according to a scan signal applied from the scan lines. The driving transistor includes a first active layer having an oxide semiconductor and a first gate electrode below the first active layer. The switching transistor includes a second active layer having a same oxide semiconductor as the oxide semiconductor of the first active layer and a second gate electrode below the second active layer. At least one of the driving transistor and the switching transistor includes an oxide layer above each of the active layers.

Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

Abstract: A memory element and methods of constructing the memory element are described. The memory element may include a bottom electrode structure having an uppermost portion of a first dimension. The memory element may further include a MTJ pillar having a bottommost portion forming an interface with the uppermost portion of the bottom electrode structure. The bottommost portion of the MTJ pillar may have a second dimension that is less than the first dimension. The memory element may further include oxidized metal particles located on an outermost sidewall of the MTJ pillar. The memory element may further include a top electrode structure located in the MTJ pillar.