Patents Examined by Eric W Jones
  • Patent number: 10096579
    Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: October 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jaspreet S. Gandhi, Michel Koopmans
  • Patent number: 10079358
    Abstract: Embodiments of the present invention disclose an array substrate comprising a base substrate and a plurality of pixel units disposed on the base substrate, the pixel unit comprising a transflective layer formed on the base substrate; a thin film transistor structure formed over the transflective layer; an organic light-emitting diode disposed in a pixel region of the pixel unit and driven by the thin film transistor structure, and in a direction away from the base substrate, the organic light-emitting diode sequentially comprising a first electrode that is transparent, an organic light-emitting layer and a second electrode for reflecting light; and a color filter, disposed between the second electrode of the organic light-emitting diode and the transflective layer; wherein the second electrode of the organic light-emitting diode and the transflective layer constitute a microcavity structure.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: September 18, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Young Suk Song, Seong Yeol Yoo, Seung Jin Choi, Hee Cheol Kim
  • Patent number: 10079276
    Abstract: An organic light emitting display panel is provided that comprises a substrate comprising an emission area and a non-emission area; a black matrix disposed on the non-emission area and comprising at least one open area that exposes at least a portion of a pattern formed on the substrate, wherein the pattern or the exposed portion of the pattern comprises a multi-layer structure comprising a conductive layer and at least one low reflective layer.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: September 18, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: JuneHo Park, EunMi Jo, Daehyun Kim
  • Patent number: 10043916
    Abstract: Embodiments of the invention disclose a thin-film transistor having a channel structure that has an increased width-length ratio and a manufacturing method thereof, a display substrate and a display device. The thin-film transistor comprises a gate, a gate insulation layer and an active layer stacked on a substrate, the active layer is formed therein with a source region, a drain region and a channel region, a surface of the active layer facing the gate insulation layer is at least partially formed with a non-planar surface in the channel region, such that the non-planar surface of the active layer has a tortuous shape in a width direction of the channel region.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: August 7, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Na Zhao, Xufei Xu, Gaofei Shi
  • Patent number: 10032922
    Abstract: A thin-film transistor, including a substrate; an active layer on the substrate; a gate electrode on the active layer; and a gate insulating layer between the active layer and the gate electrode, the active layer including a channel region; source and drain regions at opposite sides of the channel region; and lightly doped regions between the channel region and the source region and between the channel region and the drain region, the source and drain regions being doped with a first element, and the lightly doped regions being doped with a second element different from the first element.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Katsushi Kishimoto
  • Patent number: 10026790
    Abstract: An organic light-emitting display device according to one embodiment of the present disclosure includes a substrate, a thin-film transistor formed on the substrate, a planarization layer formed on the thin-film transistor, an organic light-emitting element formed on the planarization layer, the emitting element including an organic light-emitting layer and a cathode, and a lower auxiliary wiring between the organic light-emitting element and the planarization layer, the wiring electrically connected with the cathode.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: July 17, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Binn Kim, BuYeol Lee
  • Patent number: 10026920
    Abstract: An organic EL display device includes a substrate on which a plurality of driver transistors are formed, a first wiring that supplies an electric voltage in accordance with a display image via one of the driver transistors, an organic EL film that emits light, an anode electrode, and an auxiliary electrode film including a first low resistance part, a second low resistance part separated from the first low resistance part, and a high resistance part disposed between the first low resistance part and the second low resistance part. The first low resistance part is electrically connected to the first wiring and the anode electrode. The second low resistance part forms an electrostatic capacitance between the anode electrode and itself. The high resistance part has an electric resistance higher than those of the first low resistance part and the second low resistance part.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: July 17, 2018
    Assignee: Japan Display Inc.
    Inventor: Naoki Tokuda
  • Patent number: 10014483
    Abstract: The present application discloses a method of fabricating an organic thin film transistor comprising providing a substrate; forming a patterned interface modification layer on the substrate; and forming an organic semiconductor layer on a side of the interface modification layer distal to the substrate, wherein the patterned interface modification layer having a pattern of micro structure.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: July 3, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Ze Liu
  • Patent number: 9985100
    Abstract: A method for doping punch through stoppers (PTSs) includes forming fins in a monocrystalline substrate, forming a dielectric layer at a base portion between the fins and forming spacers on sidewalls of the fins down to a top portion of the dielectric layer. The dielectric layer is recessed to form gaps between the top portion of the dielectric layer and the spacer to expose the fins in the gaps. The fins are doped through the gaps to form PTSs in the fins.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Tenko Yamashita
  • Patent number: 9984917
    Abstract: A method for manufacturing a semiconductor device in accordance with various embodiments may include: forming an opening in a first region of a semiconductor substrate, the opening having at least one sidewall and a bottom; implanting dopant atoms into the at least one sidewall and the bottom of the opening; configuring at least a portion of a second region of the semiconductor substrate laterally adjacent to the first region as at least one of an amorphous or polycrystalline region; and forming an interconnect over at least one of the first and second regions of the semiconductor substrate.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: May 29, 2018
    Assignee: Infineon Technologies AG
    Inventors: Christian Kuehn, Martin Bartels, Henning Feick, Dirk Offenberg, Anton Steltenpohl, Hans Taddiken, Ines Uhlig
  • Patent number: 9978709
    Abstract: A method of producing a solder bump joint includes heating a solder bump comprising tin above a melting temperature of the solder bump, wherein the solder bumps comprises eutectic Sn—Bi compound, and the eutectic Sn—Bi compound is free of Ag. The method further includes stretching the solder bump to increase a height of the solder bump, wherein stretching the solder bump forms lamellar structures having a contact angle of less than 90°. The method further includes cooling down the solder bump.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Chun Yang, Chung-Jung Wu, Hsiao-Yun Chen, Yi-Li Hsiao, Chih-Hang Tung, Da-Yuan Shih, Chen-Hua Yu
  • Patent number: 9947892
    Abstract: An organic light-emitting display apparatus, including a lower substrate having a peripheral area, which includes a first peripheral part and a second peripheral part, and a display area between the first peripheral part and the second peripheral part; an upper substrate on the lower substrate; a sealing member between the lower substrate and the upper substrate and on the lower substrate in the peripheral area; and a first material layer between the sealing member and the lower substrate and including a first opening pattern at the first peripheral part and a second opening pattern at the second peripheral part, the second opening pattern having a smaller size than the first opening pattern.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: April 17, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Heechul Jeon
  • Patent number: 9934971
    Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: April 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
  • Patent number: 9922821
    Abstract: Provided is a technique of forming a film containing a first element and a second element on a substrate by performing a cycle a predetermined number of times. The cycle includes: (a) supplying a hydro-based precursor containing the first element and a halogen-based precursor containing the second element into a process chamber accommodating a substrate to confine the hydro-based precursor and the halogen-based precursor in the process chamber; (b) maintaining a state where the hydro-based precursor and the halogen-based precursor are confined in the process chamber; and (c) exhausting the process chamber.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: March 20, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Tsuyoshi Takeda
  • Patent number: 9917080
    Abstract: A semiconductor device with electrical overstress (EOS) protection is disclosed. The semiconductor device includes a semi-insulating layer, a first contact disposed onto the semi-insulating layer, and a second contact disposed onto the semi-insulating layer. A passivation layer is disposed onto the semi-insulating layer. The passivation layer has a dielectric strength that is greater than that of the semi-insulating layer to ensure that a voltage breakdown occurs within the semi-insulating layer within a semi-insulating region between the first contact and the second contact before a voltage breakdown can occur in the passivation layer.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: March 13, 2018
    Assignee: Qorvo US. Inc.
    Inventor: Andrew P. Ritenour
  • Patent number: 9911888
    Abstract: A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 9865660
    Abstract: An optoelectronic device which can read magnetically stored information, and convert it into optical light signals using organic or “plastic” semiconductors is described. Such a device may use OLEDs, and may be termed an “organic magneto-optic transducer” (OMOT). An OMOT device can read magnetically stored information, and convert it into optical light signals. The OMOT may provide benefits such as non-volatile storage, flexible films, reduced cost, and operation at room temperature.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: January 9, 2018
    Assignee: University of Iowa Research Foundation
    Inventors: Markus Wohlgenannt, Michael Flatte, Andrew Kent, Fujian Wang, Nicholas Harmon, Ferran Macia Bros
  • Patent number: 9865781
    Abstract: A manufacturing method for a light emitting device can include providing a bonding layer over a base, and disposing a shim plate with an opening over the bonding layer. A light emitting body is disposed over the bonding layer exposed from the opening of the shim plate. A lens is formed by approaching a die having a concave portion at its surface, to the shim plate, covering an upper surface of the light emitting body and an upper surface of the shim plate with a lens formation material within the concave portion, and then hardening the lens formation material.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: January 9, 2018
    Assignee: NICHIA CORPORATION
    Inventor: Yuta Oka
  • Patent number: 9842806
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: December 12, 2017
    Assignee: Micron Technology, Inc.
    Inventor: David S. Pratt
  • Patent number: 9842817
    Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips; and securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The wafer-level pulling method further includes softening the plurality of solder bumps; and stretching the plurality of softened solder bumps.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: December 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Chun Yang, Yi-Li Hsiao, Chih-Hang Tung, Chen-Hua Yu