Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.

Abstract: A magnetic tunnel junction device includes a first ferromagnetic layer, a tunnel barrier that is in contact with the first ferromagnetic layer, and a synthetic ferrimagnetic reference layer that is in contact with the tunnel barrier while being in the other side of the first ferromagnetic layer, in which the synthetic ferrimagnetic reference layer includes a second ferromagnetic layer that has a first magnetization direction while being in contact with the tunnel barrier, a magnetic layer that has a second magnetization direction which is anti-parallel to the first magnetization direction, and a first nonmagnetic layer that is interposed between the second ferromagnetic layer and the magnetic layer, and lateral dimensions of the magnetic layer of the synthetic ferrimagnetic reference layer are made larger than lateral dimensions of the first ferromagnetic layer and the second ferromagnetic layer.

Abstract: A structure is disclosed. The structure contains a second detector disposed above a first detector, wherein the first detector contains a first absorber layer, a first barrier layer disposed above the first absorber layer, a first contact layer disposed above the first barrier layer, and wherein the second detector contains a second contact layer disposed above the first contact layer, a second barrier layer disposed above the second contact layer, a second absorber layer disposed above the second barrier layer.

Abstract: The present application relates to an OLED panel for a lighting device and a method of manufacturing the same. An OLED panel for a lighting device includes: a substrate; a auxiliary wiring pattern having a plurality of wiring lines disposed on the substrate; a first electrode disposed on the substrate where the auxiliary wiring pattern is disposed, and having a planarized upper surface; a passivation layer disposed on the first electrode and disposed at least in an area above the auxiliary wiring pattern; an OLED emission structure disposed on the first electrode; and a second electrode disposed on the OLED emission structure. In the OLED panel for a lighting device, luminance uniformity may be improved through a dual auxiliary wiring pattern, and the upper surface of the first electrode is planarized. Accordingly, the area of the passivation layer is reduced, and thus a light-emitting area may be increased.

Abstract: Provided is a display panel. The display panel includes a base layer in which a display area where a plurality of pixels are disposed and a non-display area surrounding the display area are defined; a circuit element layer which is disposed on the base layer; an input sensing layer which is disposed on the circuit element layer; and one or more display signal pads and one or more sensing signal pads which are disposed on a sidewall of each of the base layer, the circuit element layer and the input sensing layer, wherein each of the display signal pads is electrically coupled to a display signal line disposed in the circuit element layer, and each of the sensing signal pads is electrically coupled to an input sensing line disposed in the input sensing layer.

Abstract: Disclosed herein is an OLED lighting apparatus which can compensate for high sheet resistance of a first electrode formed of a transparent conductive material while improving light extraction efficiency through enhancement in aperture ratio. For this purpose, the OLED lighting apparatus omits auxiliary wires and, instead of the auxiliary wires, includes a first auxiliary wire and a second auxiliary wire to secure low resistance. As a result, the OLED lighting apparatus can compensate for high sheet resistance of the first electrode, thereby achieving normal light emission without reduction in luminance due to current drop when implemented as a large-area high-resolution lighting apparatus.

Abstract: A display device according to the present disclosure includes a first electrode, an inorganic hole injecting and transporting layer which is formed of an inorganic material and is formed on the first electrode, at least two light emitting units including a first organic light emitting unit and a second organic light emitting unit having different luminescent colors which are formed on the inorganic hole injecting and transporting layer, an electron transport layer which is formed on the at least two organic light emitting units, and a second electrode which is formed on the electron transport layer. Furthermore, a light emitting layer of the first organic light emitting unit is formed by laminating a light emitting layer of a first luminescent color and a light emitting layer of a second luminescent color, and a light emitting layer of the second organic light emitting unit is formed of the light emitting layer of the second luminescent color.

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a first epitaxial structure and a second epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a first conductive via electrically connected to the first epitaxial structure through a conductive contact. The first conductive via is misaligned with the first epitaxial structure. The semiconductor device structure further includes a second conductive via electrically connected to the second epitaxial structure. The second conductive via is aligned with the second epitaxial structure.

Abstract: A split gate structure is disclosed. The split gate structure includes a first polysilicon, a characteristic oxide, and a second polysilicon sequentially disposed in a trench in a vertical direction upward from a bottom of the trench. An upper surface of the characteristic oxide has a height difference less than 1500 ? between a higher center portion and a lower periphery portion. The split gate structure effectively improves the breakdown performance and the IGSS performance. A power MOS device having the split gate structure and a manufacturing method of the split gate structure are also provided.

Abstract: This invention discloses a semiconductor power device formed on a semiconductor substrate comprises an active cell area and a termination area disposed near edges of the semiconductor substrate. The termination area comprises a plurality of duplicated units wherein each unit includes at least two trenches filled with a conductive trench material having a mesa area between adjacent trenches wherein the trenches and the mesa areas within each of the duplicated units are electrically shunt together. In the termination area each of the trenches in the duplicated units has a buried guard ring dopant region disposed below a bottom surface of the trenches.

Abstract: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.

Abstract: A display panel includes a flexible electrochromic substrate comprising a first flexible substrate layer, a second flexible substrate layer opposing to the first flexible substrate layer and an electrochromic part disposed between the first and second flexible substrate layers and configured to discolor in response to a driving signal, a transistor layer disposed on the flexible electrochromic substrate, the transistor layer comprising a plurality of transistors and an organic light emitting diode layer disposed on the flexible electrochromic substrate on which the transistor layer is disposed, the organic light emitting diode layer comprising a plurality of organic light emitting diodes connected to the plurality of transistors.

Abstract: An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.

Abstract: Semiconductor device assemblies having stacked semiconductor dies and electrically functional heat transfer structures (HTSs) are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a mounting surface with a base region and a peripheral region adjacent the base region. At least one second semiconductor die can be electrically coupled to the first semiconductor die at the base region. The device assembly can also include an HTS electrically coupled to the first semiconductor die at the peripheral region.

Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.

Abstract: A method and composition for producing a low k dielectric film via plasma enhanced chemical vapor deposition comprise the steps of: providing a substrate within a reaction chamber; introducing into the reaction chamber gaseous reagents including at least one structure-forming precursors comprising a silacycloalkane compound, an oxygen source, and optionally a porogen; applying energy to the gaseous reagents in the reaction chamber to induce reaction of the gaseous reagents to deposit a low k dielectric film having dielectric constant of 3.2 or less. In certain embodiments, the structure-forming precursor further comprises a hardening additive.

Abstract: A method of fabricating tantalum nitride barrier layer in an ultra low threshold voltage semiconductor device is provided. The method includes forming a high-k dielectric layer over a semiconductor substrate. Subsequently, a tantalum nitride barrier layer is formed on the high-k dielectric layer. The tantalum nitride barrier layer has a Ta:N ratio between 1.2 and 3. Next, a plurality of first metal gates is formed on the tantalum nitride barrier layer. The first metal gates are patterned, and then a second metal gate is formed on the tantalum nitride barrier layer.

Abstract: An organic light-emitting diode (OLED) display device including a display panel and an image capturing assembly, wherein the display panel comprises a base substrate and a display layer. The image capturing assembly comprises a sensor, a signal module, and a lens. The sensor is disposed in a groove of the base substrate, and a height of the sensor is greater than a depth of the groove, and an upper end of the sensor and the signal module extend into the TFT layer. An image capturing signal transmission line electrically connected to the signal module is disposed in the TFT layer. The lens is disposed in an opening of the display layer corresponding above the sensor.

Abstract: The present invention relates to new aromatic-amino functional siloxanes, which are compounds comprising one or two tail groups X2, and a linking group L of structure (2) linking each said tail group to said head group, wherein the head group X has structure (1), containing an optional organic moiety Y, wherein the attachment point of said tail group X2 through said linking group L to the head group X1, may be, at positions a, b, c, d, or e. Another aspect of this invention are compositions containing these novel aromatic amino functional siloxane. A further aspect of this invention are compositions comprised of the above novel aromatic-amino functional siloxanes, and also the composition resulting from the aging of these compositions at room temperature for about 1 day to about 4 weeks.

Abstract: In example implementations of a heterogeneous substrate, the heterogeneous substrate includes a first material having an air trench, a second material coupled to the first material, a dielectric mask on a first portion of the second material and an active region that is grown on a remaining portion of the second material. An air gap may be formed in the air trench by the second material coupled to the first material. Defects in the second material may be contained to an area below the dielectric mask and the active region may remain defect free.