Patents Examined by Erik Kielin
  • BioFET and method of manufacturing the same
    Patent number: 11320395
    Abstract: An integrated circuit device includes a device layer, an interconnect structure, a conductive layer, a passivation layer and a bioFET. The device layer has a first side and a second side and include source/drain regions and a channel region between the source/drain regions. The interconnect structure is disposed at the first side of the device layer. The conductive layer is disposed at the second side of the device layer. The passivation layer is continuously disposed on the conductive layer and the channel region and exposes a portion of the conductive layer. The bioFET includes the source/drain regions, the channel region and a portion of the passivation layer on the channel region.
    Type: Grant
    Filed: June 14, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hui Lin, Chun-Ren Cheng, Jui-Cheng Huang, Shih-Fen Huang, Tung-Tsun Chen, Yu-Jie Huang, Fu-Chun Huang
  • Method for forming insulating film, apparatus for processing substrate, and system for processing substrate
    Patent number: 11315784
    Abstract: There is provided a technique of forming an insulating film containing silicon oxide. A coating solution containing polysilazane is applied onto a wafer W, the solvent of the coating solution is volatilized, and the coating film is irradiated with ultraviolet rays in nitrogen atmosphere before performing a curing process. Dangling bonds are generated in silicon which is a pre-hydrolyzed site in polysilazane. Therefore, the energy for hydrolysis is reduced, and unhydrolyzed sites are reduced even when the temperature of the curing process is 350° C. Since efficient dehydration condensation occurs, the crosslinking rate is improved, and a dense (good-quality) insulation film is formed. By forming a protective film on the surface of the coating film to which ultraviolet rays irradiated, the reaction of dangling bonds prior to the curing process is suppressed.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: April 26, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Makoto Muramatsu, Hisashi Genjima
  • Method of making a semiconductor device including a graphene barrier layer between conductive layers
    Patent number: 11302576
    Abstract: There is provided a semiconductor device including a first conductive layer formed on a substrate; a second conductive layer serving as a wiring layer and a barrier layer provided between the first conductive layer and the second conductive layer, wherein the barrier layer is made of a graphene film, and the second conductive layer includes a metal silicide compound, the metal silicide compound being provided so as to be in contact with the graphene film constituting the barrier layer.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: April 12, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Makoto Wada, Takashi Matsumoto, Masahito Sugiura, Ryota Ifuku
  • Display panel with shielded signal lines routed around an opening area in the display panel
    Patent number: 11302767
    Abstract: A display panel includes: a substrate including an opening area, a non-display area at least partially surrounding the opening area, and a display area; a plurality of first lines, each of which includes a first bypass portion along the opening area; a plurality of second lines, each of which includes a second bypass portion along the opening area; and a shield layer overlapping at least one first bypass portion. Each of the first lines includes a first or second conductive line in the non-display area. Each of the first and second conductive lines includes the first bypass portion. The first and second conductive lines are alternately arranged and are disposed on different layers. Each of the second lines includes a third conductive line in the non-display area. Each of the third conductive lines includes the second bypass portion, and at least partially overlaps the first or second conductive line.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: April 12, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Minku Lee, Kyunghoon Kim, Mihae Kim, Changwon Jeong, Wonmi Hwang
  • Method of fabricating semiconductor device including dummy via anchored to dummy metal layer
    Patent number: 11302654
    Abstract: A method includes depositing a first dielectric layer over a substrate; forming a first dummy metal layer over the first dielectric layer, wherein the first dummy metal layer has first and second portions laterally separated from each other; depositing a second dielectric layer over the first dummy metal layer; etching an opening having an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first dummy metal layer, and a lower portion in the first dielectric layer, wherein a width of the lower portion of the opening is greater than a width of the middle portion of the opening, and a bottom of the opening is higher than a bottom of the first dielectric layer; and forming a dummy via in the opening and a second dummy metal layer over the dummy via and the second dielectric layer.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Integrated circuit packages and methods of forming same
    Patent number: 11289410
    Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Jui Kuo, Ming-Che Ho, Tzung-Hui Lee
  • Method of simultaneously forming contacts to a power rail and the source and drain regions of a FinFET
    Patent number: 11282753
    Abstract: In a method for manufacturing a semiconductor device that comprises a semiconductor fin including a source region and a drain region, which configure a field effect transistor, and a fixed potential line provided in parallel to the semiconductor fin, the method comprises: a first step of preparing an intermediate body in which an insulating layer is provided on the source region (P-type conductive region), the drain region (N-type conductive region), and the fixed potential line; and a second step of simultaneously forming contact holes leading to the source region, the drain region, and the fixed potential line, in the insulating layer.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: March 22, 2022
    Assignee: Tokyo Electron Limited
    Inventor: Kazuo Kibi
  • Display apparatus
    Patent number: 11276743
    Abstract: A display apparatus includes: a substrate including a display area in which a plurality of pixel areas is arranged, and a peripheral area adjacent to the display area and in which a pad portion including a plurality of pad electrodes is arranged; a first signal line and a second signal line in the display area on the substrate; a first connecting line electrically connected to the first signal line and connected to the pad portion, at least a portion of the first connecting line being in the display area; and a dummy line on a same layer as the first connecting line.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: March 15, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Hwan Cho, Jong Hyun Choi, Gyung Soon Park, Juchan Park, Seungmin Song, Minseong Yi
  • Power and data routing structures for organic light-emitting diode displays
    Patent number: 11251259
    Abstract: An organic light-emitting diode display may have rounded corners. A negative power supply path may be used to distribute a negative voltage to a cathode layer, while a positive power supply path may be used to distribute a positive power supply voltage to each pixel in the display. The positive power supply path may have a cutout that is occupied by the negative power supply path to decrease resistance of the negative power supply path in a rounded corner of the display. To mitigate reflections caused by the positive power supply path being formed over tightly spaced data lines, the positive power supply path may be omitted in a rounded corner of the display, a shielding layer may be formed over the positive power supply path in the rounded corner, or non-linear gate lines may be formed over the positive power supply path.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: February 15, 2022
    Assignee: Apple Inc.
    Inventors: Tiffany T. Moy, Yuchi Che, Seonpil Jang, Warren S. Rieutort-Louis, Bhadrinarayana Lalgudi Visweswaran, Jae Won Choi, Abbas Jamshidi Roudbari, Myung-Kwan Ryu, Hirokazu Yamagata, Keisuke Otsu
  • Folding display device including detachable protective film
    Patent number: 11245089
    Abstract: A display apparatus including a display module having flexibility, a glass window disposed on the display module, a protective film including an adhesive layer detachably attached on the glass window and a protecting layer disposed on the adhesive layer, a protective coating pattern disposed on an edge of an upper surface of the glass window, and a cover covering at least a portion of the edge of the glass window and configured to receive the display module, in which the protective coating pattern partially overlaps the adhesive layer of the protective film.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: February 8, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jaiku Shin, Dongjin Park, Dongwoo Seo, Sung Chul Choi
  • Semiconductor device
    Patent number: 11239120
    Abstract: A semiconductor device includes first active patterns and second active patterns on a substrate, a first source/drain region on the first active patterns, a second source/drain region on the second active patterns and a device isolation layer filling a first trench between adjacent ones of the first active patterns and a second trench between adjacent ones of the second active patterns. A liner layer is disposed on the device isolation layer between the adjacent ones of the second active patterns. The device isolation layer between the adjacent ones of the first active patterns has a recess therein under the first source/drain region and a bottom surface of the liner layer between the adjacent ones of the second active patterns is higher than the recess.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: February 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunki Min, Donghyun Roh
  • Isolation features and methods of fabricating the same
    Patent number: 11239309
    Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Wen Wu, Fu-Kai Yang, Chen-Ming B. Lee, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
  • Methods and apparatus for semi-dynamic bottom up reflow
    Patent number: 11222816
    Abstract: A method of filling structures on a substrate uses a semi-dynamic reflow process. The method may include depositing a metallic material on the substrate at a first temperature, heating the substrate to a second temperature higher than the first temperature wherein heating of the substrate causes a static reflow of the deposited metallic material on the substrate, stopping heating of the substrate, and depositing additional metallic material on the substrate causing a dynamic reflow of the deposited additional metallic material on the substrate. RF bias power may be applied during the dynamic reflow to facilitate in maintaining the temperature of the substrate.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: January 11, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Lanlan Zhong, Shirish A. Pethe, Fuhong Zhang, Joung Joo Lee, Kishor Kalathiparambil, Xiangjin Xie, Xianmin Tang
  • Method of testing and analyzing display panel
    Patent number: 11217649
    Abstract: A method for testing and analyzing a display panel, comprising: providing a display panel including a circuitry and a pixel connected to the circuitry, wherein the pixel includes a capacitor, a transistor and an electrode electrically connected to the capacitor and the transistor; measuring a first parameter of the display panel; disabling the pixel; measuring a second parameter of the display panel; and deriving a third parameter of the pixel by subtracting the second parameter from the first parameter.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: January 4, 2022
    Assignee: Star Technologies, Inc.
    Inventor: Choon Leong Lou
  • Synthetic diamond plates
    Patent number: 11211306
    Abstract: A synthetic diamond plate comprising a polygonal plate formed of synthetic diamond material, the polygonal plate of synthetic diamond material having a thickness in a range 0.4 mm to 1. mm, and rounded corners having a radius of curvature in a range 1 mm to 6 mm. A mounted synthetic diamond plate is also disclosed comprising a polygonal synthetic diamond plate as described and a base to which the polygonal synthetic diamond plate is bonded, wherein the base comprises a cooling channel. An array of mounted synthetic diamond plates is also described, comprising a plurality of mounted synthetic diamond plates described above, wherein the cooling channels of the mounted synthetic diamond plates are linked to form a common cooling channel across the array of mounted synthetic diamond plates.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 28, 2021
    Assignee: ELEMENT SIX TECHNOLOGIES LIMITED
    Inventors: Julian Ellis, John Brandon, Francis Mark Reininger
  • Organic electroluminescent device and an organic electroluminescent apparatus
    Patent number: 11205763
    Abstract: An organic electroluminescent device and an organic electroluminescent apparatus are disclosed. The organic electroluminescent device includes a first electrode layer, a first carrier functional layer, a light-emitting layer and a second electrode layer stacked in sequence, wherein a P-doped layer is arranged between the first carrier functional layer and the light-emitting layer. Thus the energy level bending of an interface between the first carrier functional layer and the light-emitting layer is modified, and the hole injection potential barrier at the interface between the two is reduced, thereby effectively reducing the turn-on voltage of the organic electroluminescent device.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: December 21, 2021
    Assignee: Yungu (Gu'an) Technology Co., Ltd.
    Inventors: Weiwei Li, Lin He, Mengzhen Li, Jingwen Tian, Tiantian Li
  • Image sensor device and method
    Patent number: 11201183
    Abstract: A system and method for forming pixels in an image sensor is provided. In an embodiment, a semiconductor device includes an image sensor including a first pixel region and a second pixel region in a substrate, the first pixel region being adjacent to the second pixel region. A first anti-reflection coating is over the first pixel region, the first anti-reflection coating reducing reflection for a first wavelength range of incident light. A second anti-reflection coating is over the second pixel region, the second anti-reflection coating reducing reflection for a second wavelength range of incident light that is different from the first wavelength range.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chang Chu, Yeur-Luen Tu, Cheng-Yuan Tsai
  • Composition for forming silica layer, silica layer and electronic device incorporating silica layer
    Patent number: 11201052
    Abstract: Disclosed is a composition for forming a silica layer including perhydropolysilazane (PHPS) and a solvent, wherein in an 1H-NMR spectrum of the perhydropolysilazane (PHPS) in CDCl3, when a peak derived from N3SiH1 and N2SiH2 is referred to as Peak 1 and a peak derived from NSiH3 is referred to as Peak 2, a ratio (P1/(P1+P2)) of an area (P1) of Peak 1 relative to a total area (P1+P2) of the Peak 1 and Peak 2 is greater than or equal to 0.77, and when an area from a minimum point between the peaks of Peak 1 and Peak 2 to 4.78 ppm is referred to as a Region B and an area from 4.78 ppm to a minimum point of Peak 1 is referred to as a Region A of the area of Peak 1, a ratio (PA/PB) of an area (PA) of Region A relative to an area (PB) of Region B is greater than or equal to about 1.5.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: December 14, 2021
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Seungwoo Jang, Taeksoo Kwak, Jin-Hee Bae, Hyeonsu Jo, Euihyun Kim, Kunbae Noh, Jun Sakong, Chungheon Lee, Wanhee Lim, Byeonggyu Hwang
  • Method of manufacturing a semiconductor device having redistribution layer including a dielectric layer made from a low-temperature cure polyimide
    Patent number: 11177165
    Abstract: A method of manufacturing a semiconductor device includes the step of positioning a patterned mask over a dielectric layer. The dielectric layer comprises a low-temperature cure polyimide. The method further includes the steps of exposing a first surface of the dielectric layer through the patterned mask to an I-line wavelength within an I-line stepper, and developing the dielectric layer to form an opening.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Hung-Jui Kuo
  • Image sensor with pad structure
    Patent number: 11177309
    Abstract: The present disclosure relates to an image sensor with a pad structure formed during a front-end-of-line process. The pad structure can be formed prior to formation of back side deep trench isolation structures and metal grid structures. An opening is formed on a back side of the image sensor device to expose the embedded pad structure and to form electrical connections.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang, Yin-Chieh Huang