Abstract: A curable silicone composition is disclosed. The curable silicone composition comprises: (A) a linear organopolysiloxane having at least two alkenyl groups and at least one aryl group in a molecule; (B) a branched organopolysiloxane represented by the average unit formula; (C) an organosiloxane having at least two silicon atom-bonded hydrogen atoms in a molecule; and (D) a hydrosilylation reaction catalyst. The curable silicone composition forms a cured product having good mechanical properties and good retention of transparency under conditions of high temperature.

Abstract: An approach providing a semiconductor wiring structure with a self-aligned top via on a first metal line and under a second metal line. The semiconductor wiring structure includes a plurality of first metal lines in a bottom portion of a first dielectric material. The semiconductor wiring structure includes a top via in a top portion of the first dielectric material, where the top via is over a first metal line of the plurality of first metal lines. The semiconductor wiring structure includes a second dielectric material above each of the plurality of first metal lines except the first metal line of the plurality of first metal lines. Furthermore, the semiconductor wiring structure includes a second metal line above the top via, wherein the second metal line is in a third dielectric material and a hardmask layer that is under the third dielectric material.

Abstract: A semiconductor structure manufacturing method according to the embodiments of the present application includes the following steps of: providing a semiconductor substrate; forming a first reaction layer on the semiconductor substrate; forming a second reaction layer on the first reaction layer; and thermally reacting at least a portion of the first reaction layer with at least a portion of the second reaction layer, to form an amorphous diffusion barrier layer. This amorphous diffusion barrier layer is an amorphous body with no grain boundary therein. As a result, the diffusion path for metal atoms is cut off, thereby improving the barrier effect of the barrier layer efficiently and solving the circuit performance issue caused by metal atom diffusion.

Abstract: An IC includes a source region and a drain region in a semiconductor layer. A channel region is between the source region and the drain region. A sensing well is on a back surface of the semiconductor layer and over the channel region. An interconnect structure is on a front surface of the semiconductor layer opposite the back surface of the semiconductor layer. A biosensing film lines the sensing well and contacts a bottom surface of the sensing well that is defined by the semiconductor layer. A coating of selective binding agent is over the biosensing film and configured to bind with a cardiac cell.

Abstract: An IC includes a source region and a drain region in a semiconductor layer. A channel region is between the source region and the drain region. A sensing well is on a back surface of the semiconductor layer and over the channel region. An interconnect structure is on a front surface of the semiconductor layer opposite the back surface of the semiconductor layer. A biosensing film lines the sensing well and contacts a bottom surface of the sensing well that is defined by the semiconductor layer. A coating of selective binding agent is over the biosensing film and configured to bind with a cardiac cell.

Abstract: A system and method for forming pixels in an image sensor is provided. In an embodiment, a semiconductor device includes an image sensor including a first pixel region and a second pixel region in a substrate, the first pixel region being adjacent to the second pixel region. A first anti-reflection coating is over the first pixel region, the first anti-reflection coating reducing reflection for a first wavelength range of incident light. A second anti-reflection coating is over the second pixel region, the second anti-reflection coating reducing reflection for a second wavelength range of incident light that is different from the first wavelength range.

Abstract: A method for manufacturing a semiconductor memory includes: providing a portion to be processed, and performing a preset process step on the portion to be processed at least after a minimum waiting time; before performing the preset process step, performing a thermal oxidation process on the portion to be processed; and before performing the preset process step, performing a cleaning process, the cleaning process being used to remove oxides from the surface of the portion to be processed, the oxides being wholly or partly generated by the thermal oxidation process.

Abstract: A method includes obtaining an active feature layer having a first surface bearing one or more active feature areas. A first capacitor plate of a first capacitor is formed on an interior surface of a cap. A second capacitor plate of the first capacitor is formed on an exterior surface of the cap. The first capacitor plate of the first capacitor overlays and is spaced apart from the second capacitor plate of the first capacitor along a direction that is orthogonal to the exterior surface of the cap to form the first capacitor. The cap is coupled with the first surface of the active feature layer such that the second capacitor plate of the first capacitor is in electrical communication with at least a first active feature of the active feature layer. The cap is bonded with the passive layer substrate.

Abstract: Embodiments of the present application relate to a method for manufacturing a semiconductor structure, includes: forming a contact metal layer on a silicon substrate; performing a plasma treatment process, and forming an oxygen isolation layer on a surface of the contact metal layer; and performing a silicidation reaction process, and converting the contact metal layer into a metal silicide layer.

Abstract: Methods for selectively depositing on metallic surfaces are disclosed. Some embodiments of the disclosure utilize a hydrocarbon having at least two functional groups, at least one functional group selected from amino groups, hydroxyl groups, ether linkages or combinations thereof to form a self-assembled monolayer (SAM) on metallic surfaces.

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.

Abstract: A method of fabricating a light emitting device comprises providing a mold having an unpolished surface with an arithmetic mean roughness Ra in a range from 0.1 ?m to 10 ?m, depositing a thin polymer film over the surface of the mold, wherein the film has a thickness in a range from 1 ?m to 100 ?m, positioning a light emitting body onto the thin polymer film, wherein the light emitting body includes an anode, a cathode, and a light emitting layer positioned between the anode and the cathode, and separating the thin polymer film with the light emitting body from the mold. A light emitting device is also described.

Abstract: A method for dielectric filling of a feature on a substrate yields a seamless dielectric fill with high-k for narrow features. In some embodiments, the method may include depositing a metal material into the feature to fill the feature from a bottom of the feature wherein the feature has an opening ranging from less than 20 nm to approximately 150 nm at an upper surface of the substrate and wherein depositing the metal material is performed using a high ionization physical vapor deposition (PVD) process to form a seamless metal gap fill and treating the seamless metal gap fill by oxidizing/nitridizing the metal material of the seamless metal gap fill with an oxidation/nitridation process to form dielectric material wherein the seamless metal gap fill is converted into a seamless dielectric gap fill with high-k dielectric material.

Abstract: There is provided a technique of forming an insulating film containing silicon oxide. A coating solution containing polysilazane is applied onto a wafer W, the solvent of the coating solution is volatilized, and the coating film is irradiated with ultraviolet rays in nitrogen atmosphere before performing a curing process. Dangling bonds are generated in silicon which is a pre-hydrolyzed site in polysilazane. Therefore, the energy for hydrolysis is reduced, and unhydrolyzed sites are reduced even when the temperature of the curing process is 350° C. Since efficient dehydration condensation occurs, the crosslinking rate is improved, and a dense (good-quality) insulation film is formed. By forming a protective film on the surface of the coating film to which ultraviolet rays irradiated, the reaction of dangling bonds prior to the curing process is suppressed.

Abstract: The invention provides a facile process for preparing various Group VI precursor compounds useful in the vapor deposition of such Group VI metals onto solid substrates, especially microelectronic semiconductor device substrates. The process provides an effective means to obtain such volatile materials, which can then be sources of molybdenum, chromium, or tungsten-containing materials to be deposited on such substrates. Additionally, the invention provides a method for vapor deposition of such compounds onto microelectronic device substrates.

Abstract: A electronic device and a fabrication method is provided. The electronic device having a first electrode and a second electrode. A nano-gap is formed between first and second electrode. The first electrode, the second electrode and the gap may be located in the same layer of the device.

Abstract: A display device according to embodiments of the present disclosure includes a display panel, a protection member to protect the display panel, and an adhesive member between the display panel and the protection member to couple the display panel to the protection member. The display panel may include a plurality of pixels to display an image, and the adhesive member may include an adhesive agent and an anti-static agent dispersed in the adhesive agent. The anti-static agent may include halogen ions, and a content of halogen ions with respect to a total weight of the adhesive agent may be within a range (e.g., from about 1 ppm to about 1000 ppm) capable of reducing stain failures caused by static electricity, without causing corrosion of driving lines in the display.

Abstract: A semiconductor device has a substrate and a first semiconductor die disposed over the substrate. A first metal frame is disposed over the substrate around the first semiconductor die. A first metal lid is disposed over the first metal frame. A flap of the first metal lid includes an elastic characteristic to latch onto the first metal frame. An edge of the flap can have a castellated edge. A recess in the first metal frame and a protrusion on the first metal lid can be used to latch the first metal lid onto the first metal frame. A second metal frame and second metal lid can be disposed over an opposite surface of the substrate from the first metal frame.

Abstract: A gas sensor and methods for producing the same are disclosed. The gas sensor of the present disclosure includes a bulk silicon layer, comprising a controllable inversion layer, an oxide layer on top of the bulk silicon layer, wherein the controllable inversion layer is located at an interface of the bulk silicon layer and the oxide layer, and a sensing layer on the oxide layer, wherein a sensitivity of the sensing layer is a function the controllable inversion layer.