Patents Examined by Erik Kielin
  • Patent number: 10510561
    Abstract: In accordance with an embodiment a method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Yu Tsai, Tsung-Shang Wei, Yu-Sheng Lin, Wen-Chih Chiou, Shin-Puu Jeng
  • Patent number: 10504972
    Abstract: An organic light emitting display panel and a method for manufacturing the same are provided. The organic light emitting display panel includes: an organic light emitting element array substrate; a thin film encapsulation layer covering the organic light emitting element array substrate and including at least one inorganic layer and at least one organic layer; a wettability adjustment layer disposed on an organic layer or inorganic layer of the thin film encapsulation layer and including a plurality of wettability adjustment pattern zones and a plurality of hollow zones, and touch electrodes made of metal. The touch electrodes are in a meshed shape and disposed in the hollow zones. A wetting angle between material of the touch electrodes and the wettability adjustment pattern zones is greater than a wetting angle between the material of the touch electrodes and the organic layer or the inorganic layer.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 10, 2019
    Assignees: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventor: Yu Cai
  • Patent number: 10505102
    Abstract: A semiconductor device includes a substrate, a semiconductor die attached to the substrate, and an encapsulation material. The semiconductor die includes a sensing element. The encapsulation material encapsulates the semiconductor die and a portion of the substrate. The encapsulation material defines a through-hole to receive a conductive element. The sensing element may include a magnetic field sensor to sense a magnetic field generated by the conductive element.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: December 10, 2019
    Assignee: Infineon Technologies AG
    Inventors: Volker Strutz, Klaus Elian, Cyrus Ghahremani, Rainer Markus Schaller
  • Patent number: 10504990
    Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Wen Wu, Fu-Kai Yang, Chen-Ming Lee, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
  • Patent number: 10497807
    Abstract: The present disclosure provides PMOS transistors and fabrication methods thereof. An exemplary fabrication process of a PMOS transistor includes providing a semiconductor substrate having a surface; forming a gate structure on the surface of the semiconductor substrate; forming SiGe regions in the surface of the semiconductor substrate at two sides of the gate structure by implanting Ge ions into the semiconductor substrate; forming sidewalls on side surfaces of the gate structure and portions of surfaces of the SiGe regions close to the gate structure; removing portions of the SiGe regions at two sides of the gate structure to expose portions of the semiconductor substrate; forming trenches in the semiconductor substrate by etching the exposed portions of the semiconductor substrate at the two sides of the sidewalls; and forming source/drain regions by filling the trenches with a compressive stress material.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: December 3, 2019
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Meng Zhao
  • Patent number: 10483264
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: November 19, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
  • Patent number: 10483213
    Abstract: Many integrated circuit die are fabricated on a wafer. Each die includes integrated functional circuitry with an array of fuse elements that are visible to optical inspection. An electrical wafer sort is performed to test the integrated functional circuitry of each die. The array of fuse elements for each die on the wafer are programmed through the electrical wafer sort process with data bits defining a die identification that specifies a location of the die on the wafer. The die is then encapsulated in a package. In the event of package failure, a decapsulation is performed to access the die. Optical inspection of the array of fuse elements is then made to extract the die identification.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: November 19, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giona Fucili, Agostino Mirabelli, Lorenzo Papillo
  • Patent number: 10464935
    Abstract: The field of the DISCLOSURE lies in active materials for organic image sensors. The present disclosure relates to naphthalene diimide-based molecules and naphthalene diimide dimer-based molecules. The present disclosure relates to transparent N materials and/or to transparent P materials including the molecule(s) according to the present disclosure and their use in absorption layer(s), photoelectric conversion layer(s) and/or an organic image sensor and methods for their synthesis. The present disclosure also relates to photoelectric conversion layer(s) including an active material according to the present disclosure, to a device, including active material(s) according to the present disclosure or photoelectric conversion layer(s) according to the present disclosure. Moreover, the present disclosure relates to an organic image sensor including photoelectric conversion layer(s) according to the present disclosure.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: November 5, 2019
    Assignee: Sony CORPORATION
    Inventors: Silvia Rosselli, Nikolaus Knorr, Tzenka Miteva, Gabriele Nelles, Vitor Deichmann, David Danner, William E. Ford, Dennis Chercka, Vladimir Yakutkin, Lars-Peter Scheller
  • Patent number: 10466126
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to pressure sensors and methods of manufacture. The structure includes: a top membrane of semiconductor material having edges defined by epitaxial material and a liner material; a back gate under the top membrane; and a cavity defined between the top membrane and the back gate.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Juergen Faul, Frank Jakubowski
  • Patent number: 10468587
    Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Yen Chou, Fu-Ting Sung, Yao-Wen Chang, Shih-Chang Liu
  • Patent number: 10446454
    Abstract: A semiconductor device package comprises a carrier having a through hole. A lid is over the carrier and comprises a first side wall, a second side wall, and a connection wall. The second side wall is opposite the first side wall, and the connection wall is between the first side wall and the second side wall. The lid and the carrier form a plurality of chambers. The first side wall, the second side wall and the connection wall form a space to fluidly connect the plurality of chambers.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: October 15, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-An Fang, Ying-Chung Chen, Cheng-Ling Huang
  • Patent number: 10411055
    Abstract: A sensor package structure includes a substrate, a sensor chip, a plurality of wires, a supporting frame, a transparent cover, and a molding compound. The substrate includes a chip bonding region and a plurality of first pads outside the chip bonding region. The sensor chip is disposed on the chip bonding region, and includes a sensing region and a plurality of second pads. Each wire has two opposite ends respectively connected to one of the first pads and one of the second pads. The supporting frame is arranged above the substrate and/or the sensor chip and includes a positioning portion. The transparent cover is fixed in position above the sensor chip by the positioning portion so as to maintain a vertical distance there-between. The molding compound fills the space in-between the substrate and the supporting frame and covers a part of an upper surface of the supporting frame.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: September 10, 2019
    Assignee: KINGPAK TECHNOLOGY INC.
    Inventors: Chun-Hua Chuang, Wen-Chung Huang, Chung-Hsien Hsin, Chen-Pin Peng, Li-Chun Hung
  • Patent number: 10381302
    Abstract: An interposer includes a first redistribution layer, an organic substrate, a capacitor, a hard mask layer, a conductive pillar, and a second redistribution layer. The organic substrate is on the first redistribution layer. The capacitor is embedded in the organic substrate and includes a first electrode layer, a second electrode layer, and a capacitor dielectric layer between the first electrode layer and the second electrode layer. The first electrode layer electrically connects with the first redistribution layer. The hard mask layer is on the organic substrate. The conductive pillar is embedded in the organic substrate and the hard mask layer and electrically connects with the first redistribution layer. The second redistribution layer is on the hard mask layer and electrically connects with the second electrode layer and the conductive pillar.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Shih-Fan Kuan, Tieh-Chiang Wu
  • Patent number: 10374069
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening having sidewalls lined with an insulating sheath. A portion of the insulating sheath adjacent the base region is removed and a base contact region is formed by epitaxial material grown from a portion of the base region exposed by removal of the portion of the insulating sheath.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: August 6, 2019
    Assignee: STMicroelectronics SA
    Inventor: Pascal Chevalier
  • Patent number: 10361300
    Abstract: A vertical FET with asymmetrically positioned source region and drain region is provided. The source region of the vertical FET is separated from a gate electrode by a gate dielectric and the drain region of the vertical FET is separated from the gate electrode by a drain spacer formed therebetween.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10355042
    Abstract: There is provided solid-state imaging devices and methods of forming the same, the solid-state imaging devices including: a semiconductor substrate; a glass substrate; an adhesion layer provided between the semiconductor substrate and the glass substrate; and a warpage correction film provided adjacent to one of the semiconductor substrate and the glass substrate.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: July 16, 2019
    Assignee: Sony Corporation
    Inventor: Hiroyasu Matsugai
  • Patent number: 10323124
    Abstract: A polymer including a moiety represented by Chemical Formula 1, an organic layer composition including the polymer, an organic layer manufactured from the organic layer composition, and a method of forming patterns using the organic layer composition are provided. The definitions of the Chemical Formula 1 are the same as defined in the detailed description.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: June 18, 2019
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Youn-Hee Nam, Seung-Hyun Kim, Hyo-Young Kwon, Sung-Hwan Kim, Ran Namgung, Soo-Hyoun Mun, Dominea Rathwell, Hyun-Ji Song, Hyeon-Il Jung, Yu-Mi Heo
  • Patent number: 10312157
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Patent number: 10312239
    Abstract: According to one embodiment, a memory includes: a bit line; a source line; a pillar extending in a first direction and including an oxide semiconductor layer; first, second and third layers arranged along the first direction and opposed to a side of the pillar; a memory cell at an intersection between the first layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor at an intersection between the second layer and the pillar; and a second transistor at an intersection between the third layer and the pillar. A first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: June 4, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tsutomu Tezuka, Fumitaka Arai, Keiji Ikeda, Tomomasa Ueda, Nobuyoshi Saito, Chika Tanaka, Kentaro Miura
  • Patent number: 10283712
    Abstract: Painted circuit devices, methods, and systems are disclosed. In some implementations, painted circuit devices are created using multiple layers of electrically conductive paint. In one aspect, a painted circuit includes a substrate and one or more paint layer applied to the substrate, where the one or more paint layers each form an electrical component of the painted circuit. A given paint layer of the one or more paint layers can include a conductive paint formulation having a resistance that is defined by a concentration of conductive material that is included in the conductive paint formulation and a thickness of the given paint layer, and lower concentrations of the conductive material included in the conductive paint formulation provide a higher resistance than higher concentrations of conductive material.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: May 7, 2019
    Assignee: Google LLC
    Inventors: Katy Kasmai, Haydn Kirk Vestal