Abstract: In certain embodiments, a method for processing a substrate includes applying a surface treatment to selected surfaces of the substrate. The substrate has a non-planar topography including structures defining recesses. The method further includes depositing a fill material on the substrate by spin-on deposition. The surface treatment directs the fill material to the recesses and away from the selected surfaces to fill the recesses with the fill material without adhering to the selected surfaces. The method further includes removing the surface treatment from the selected surfaces of the substrate and depositing a planarizing film on the substrate by spin-on deposition. The planarizing film is deposited on the selected surfaces and top surfaces of the fill material.

Abstract: A light emitting device may include a first electrode, a second electrode opposite to the first electrode, and an emission layer disposed between the first electrode and the second electrode. The emission layer may include a manganese complex compound and a quantum dot. It is possible to improve life span and light emitting efficiency characteristics of the light emitting device.

Abstract: A method of forming vertical fins on a substrate at the same time, the method including, forming a mask segment on a first region of the substrate while exposing the surface of a second region of the substrate, removing a portion of the substrate in the second region to form a recess, forming a fin layer in the recess, where the fin layer has a different material composition than the substrate, and forming at least one vertical fin on the first region of the substrate and at least one vertical fin on the second region of the substrate, where the vertical fin on the second region of the substrate includes a fin layer pillar formed from the fin layer and a substrate pillar.

Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.

Abstract: A display device according to embodiments of the present disclosure includes a display panel, a protection member to protect the display panel, and an adhesive member between the display panel and the protection member to couple the display panel to the protection member. The display panel may include a plurality of pixels to display an image, and the adhesive member may include an adhesive agent and an anti-static agent dispersed in the adhesive agent. The anti-static agent may include halogen ions, and a content of halogen ions with respect to a total weight of the adhesive agent may be within a range (e.g., from about 1 ppm to about 1000 ppm) capable of reducing stain failures caused by static electricity, without causing corrosion of driving lines in the display.

Abstract: A method includes obtaining an active feature layer having a first surface bearing one or more active feature areas. A first capacitor plate of a first capacitor is formed on an interior surface of a cap. A second capacitor plate of the first capacitor is formed on an exterior surface of the cap. The first capacitor plate of the first capacitor overlays and is spaced apart from the second capacitor plate of the first capacitor along a direction that is orthogonal to the exterior surface of the cap to form the first capacitor. The cap is coupled with the first surface of the active feature layer such that the second capacitor plate of the first capacitor is in electrical communication with at least a first active feature of the active feature layer. The cap is bonded with the passive layer substrate.

Abstract: An image sensor includes a first transfer gate formed over a substrate, and including a first projection; a second transfer gate formed over the substrate, neighboring the first transfer gate, and including a second projection; and a floating diffusion formed in the substrate, and partially overlapping with the first transfer gate and the second transfer gate, wherein the first projection and the second projection face each other.

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.

Abstract: An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.

Abstract: Methods and apparatuses for selective deposition of metal oxides on metal surfaces relative to dielectric surfaces are provided. Selective deposition is achieved by exposing metal and dielectric surfaces to a blocking reagent capable of forming a hydrolyzable bond with metal while forming a non hydrolyzable bond with the dielectric, and dipping the surfaces in water to cleave the hydrolyzable bond and leave a blocked surface on the dielectric surface, followed by depositing metal oxide selectively on the metal surface relative to the dielectric surface. Blocking reagents are deposited by wet or dry techniques and may include an alkylaminosilane or alkylchlorosilane as examples.

Abstract: A photoelectric conversion element according to the disclosure includes: a first electrode and a second electrode that are disposed to face each other; and a photoelectric conversion layer that is provided between the first electrode and the second electrode, and contains at least one kind of polycyclic aromatic compound represented by any one of the following general formula (1), the following general formula (2), and the following general formula (3):

Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form shield tunnels in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of blowing air to each device chip from the polyester sheet side to push up each device chip through the polyester sheet and picking up each device chip from the polyester sheet.

Abstract: An organic light-emitting display panel and a display device are provided. The organic light-emitting display panel includes: a plurality of touch electrodes extending in a first direction and arranged in a second direction; and a plurality of first leads one-to-one corresponding to the plurality of touch electrodes. The first leads are made of a transparent conductive material. The first leads are located in a different layer from the touch electrodes. An insulation layer is disposed between the film layers where the first leads and the touch electrodes are located. Each first lead at least partially overlaps with a corresponding touch electrode in a direction perpendicular to a plane of the organic light-emitting display panel, and is electrically connected to the corresponding touch electrode through a through hole in the insulation layer. The first lead extends in the first direction and is arranged in the second direction.

Abstract: An image sensor includes a first transfer gate formed over a substrate, and including a first projection; a second transfer gate formed over the substrate, neighboring the first transfer gate, and including a second projection; and a floating diffusion formed in the substrate, and partially overlapping with the first transfer gate and the second transfer gate, wherein the first projection and the second projection face each other.

Abstract: A semiconductor device that is miniaturized and highly integrated is provided. One embodiment of the present invention is a semiconductor device including a first insulator, a second insulator, a first conductor, a second conductor, and a semiconductor layer; the first insulator includes an opening exposing the semiconductor layer; the first conductor is provided in contact with the semiconductor layer at a bottom of the opening; the second insulator is provided in contact with a top surface of the first conductor and a side surface in the opening; the second conductor is provided in contact with the top surface of the first conductor and in the opening with the second insulator therebetween; and the second insulator has a barrier property against oxygen.

Abstract: The invention provides a facile process for preparing various Group VI precursor compounds useful in the vapor deposition of such Group VI metals onto solid substrates, especially microelectronic semiconductor device substrates. The process provides an effective means to obtain such volatile materials, which can then be sources of molybdenum, chromium, or tungsten-containing materials to be deposited on such substrates. Additionally, the invention provides a method for vapor deposition of such compounds onto microelectronic device substrates.

Abstract: The present disclosure generally relates to methods for processing of substrates, and more particularly relates to methods for forming a metal gapfill. In one implementation, the method includes forming a metal gapfill in an opening using a multi-step process. The multi-step process includes forming a first portion of the metal gapfill, performing a sputter process to form one or more layers on one or more side walls, and growing a second portion of the metal gapfill to fill the opening with the metal gapfill. The metal gapfill formed by the multi-step process is seamless, and the one or more layers formed on the one or more side walls seal any gaps or defects between the metal gapfill and the side walls. As a result, fluids utilized in subsequent processes do not diffuse through the metal gapfill.

Abstract: Process chamber lid assemblies and process chambers comprising same are described. The lid assembly has a housing with a gas dispersion channel in fluid communication with a lid plate. A contoured bottom surface of the lid plate defines a gap to a top surface of a gas distribution plate. A pumping channel is formed between an upper outer peripheral contour of the gas distribution plate and the lid plate.

Abstract: The present invention relates to the field of chemical industry, and discloses organosilicone micro-mesoporous ultra-low dielectric thin films and preparation methods therefor. A structural formula of a POSS-based organosilane precursor in the thin film is as follows: where n is 12, 16, 18, 20, or 22, and X is CH3 or CH2CH3. The preparation method includes the following steps: dissolving a certain amount of the POSS-based precursor in an organic solvent at a room temperature; adding an appropriate amount of a photoacid generator, after uniformly stirring, spraying a mixed liquid to form a film on a substrate; placing the substrate under a light-emitting diode lamp for irradiating for a preset time after the organic solvent is completely evaporated; then placing the substrate in N,N-dimethylformamide for undergoing a transesterification reaction with fluoroalkyl alcohol for 24-72 h; and washing and drying to obtain the organosilicone micro-mesoporous ultra-low dielectric thin film.

Abstract: Methods and devices for forming painted circuits using multiple layers of electrically conductive paint. In one aspect, a painted circuit includes a substrate (111) and one or more paint layer (106, 108, 110, 112, 114, 116, 120, 122) applied to the substrate, where the one or more paint layers each form an electrical component of the painted circuit. A given paint layer of the one or more paint layers includes a conductive paint formulation having a resistance that is defined by a concentration of conductive material that is included in the conductive paint formulation and a thickness of the given paint layer, and lower concentrations of the conductive material included in the conductive paint formulation provide a higher resistance than higher concentrations of conductive material.