Abstract: A finFET structure, and method of forming such structure, in which a germanium enriched nanowire is located in the channel region of the FET, while simultaneously having silicon-germanium fin in the source/drain region of the finFET.

Abstract: Provided is an infrared detecting device with high SNR. The infrared detecting device includes: a semiconductor substrate; a first compound semiconductor layer; a light receiving layer formed on the first compound semiconductor layer and containing at least In and Sb and having a predetermined range(s) of Al or Al and Ga proportion(s); a third compound semiconductor layer; and a second compound semiconductor layer containing at least In, Al, and Sb and having a predetermined range(s) of Al or Al and Ga proportion(s), in which the first compound semiconductor layer includes, in the stated order, a first A layer, a first B layer, and a first C layer, each containing at least In and Sb and having a predetermined range(s) of Al or Al and Ga proportion(s), and the proportion(s) of the Al composition or the Al composition and the Ga composition of each layer satisfy a predetermined relation(s).

Abstract: The present disclosure relates to a semiconductor device, an operation method of a semiconductor device, and a manufacturing method of a semiconductor device which are capable of minimizing influence of a gate length variation on a circuit characteristic and increasing a good product ratio (yield) in a product sorting test. A ring oscillator configured such that the plurality of inverters is connected in a ring-like form, and gate capacitors of the transistors are connected to respective output terminals of the plurality of inverters as a load capacitor outputs an oscillating signal, the ring oscillator is configured with a plurality of transistors having the same gate length, and at least two or more ring oscillators including a plurality of transistors having different gate lengths are configured.

Abstract: A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.

Abstract: A display device includes a first substrate and a flexible circuit board. Data lines, scan lines, thin film transistors, gate contacts, and source contacts are disposed on the first substrate. The scan lines are intersected with the data lines. The thin film transistors are respectively connected to the data lines and the scan lines. The gate contacts are connected to the scan lines. The source contacts are connected to the data lines. The display device further includes first conductive patterns disposed on a side of the first substrate, and the first conductive patterns are connected to at least some of the gate contacts on the side of the first substrate. First pads of the flexible circuit board are connected to the first conductive patterns.

Abstract: A method for manufacturing an electronic device includes: providing a semiconductor carrier including first and second vertically integrated electronic structures laterally spaced apart from each other, an electrical connection layer disposed over a first side of the semiconductor carrier and electrically connecting the first and second vertically integrated electronic structures with each other; mounting the semiconductor carrier on a support carrier with the first side of the semiconductor carrier facing the support carrier; thinning the semiconductor carrier from a second side opposite the first side; and removing material of the semiconductor carrier in a separation region between the first and second vertically integrated electronic structures to separate a first semiconductor region of the first vertically integrated electronic structure from a second semiconductor region of the second vertically integrated electronic structure with the first and second vertically integrated electronic structures remain

Abstract: A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement.

Abstract: An optical device includes a light-emitting unit and a light-receiving unit. The light-emitting unit emits light forward in a first direction. The light-emitting unit has a light-emitting-side through hole that causes light traveling backward in the first direction to pass through. The light-receiving unit is arranged backward in the first direction relative to the light-emitting unit. The light-receiving unit has a light receiver that receives light after the light has passed through the light-emitting-side through hole.

Abstract: A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.

Abstract: A display device is provided. The display device includes a supporting film and a flexible substrate disposed on the supporting film. The display device also includes a driving layer disposed on the flexible substrate, and a conductive pad disposed on the driving layer. The display device further includes a light-emitting diode disposed on the conductive pad and electrically connected to the conductive pad, wherein the supporting film has a first hardness, the flexible substrate has a second hardness, and the first hardness is greater than or equal to the second hardness.

Abstract: The present invention discloses a three-dimensional package structure. The first conductive element comprises a top surface, a bottom surface and a lateral surface. The conductive pattern disposed on the top surface of the first conductive element. A second conductive element is disposed on the conductive pattern. The first conductive element is electrically connected to the conductive pattern, and the second conductive element is electrically connected to the conductive pattern. In one embodiment, the shielding layer is a portion of the patterned conductive layer.

Abstract: A base carrier configured to carry a flexible base of a flexible display panel is provided. The flexible display panel includes a display region and a circuit bonding region. A surface of an area of the base carrier corresponding to the display region is smooth, and a surface of an area of the base carrier corresponding to the circuit bonding region is formed with a plurality of micro-grooves. The structure of the base carrier is such that when the flexible base is separated from the base carrier, the amount of laser required for peeling in each of the display region and the circuit bonding region are the same and such that the base carrier can be separated from the flexible display panel by performing the laser scanning once, which simplifies the processes.

Abstract: A method for manufacturing a printed board includes steps of; providing a starting board comprising a base member having a plate-like shape, having an upper surface and a lower surface opposite the upper surface, and having an insulation property, a first metal layer disposed on the upper surface, and a second metal layer disposed on the lower surface; and laser machining a through-hole penetrating the starting board in a thickness direction of the starting board by irradiating a laser beam irradiation area of the starting board with a laser beam from a side of the starting board on which side the first metal layer is disposed. The method further includes a step of etching the second metal layer so as to remove a portion of the second metal layer located in the laser beam irradiation area, prior to the step of laser machining.

Abstract: An organic light emitting diode display includes an organic light emitting display panel including an upper surface receiving first incident light from outside and a lower surface opposite to the upper surface, a light transmission preventing layer including a base layer and an adhesive layer which is between the base layer and the organic light emitting display panel and bonded thereto, the adhesive layer including a facing surface facing the lower surface and a plurality of patterns protruded from the facing surface toward the organic light emitting display panel to define a plurality of gaps between the lower surface and the facing surface. The adhesive layer includes a light blocking material blocking second incident light which passes through the organic light emitting display panel to the light transmission preventing layer from among the first incident light received by the upper surface of the organic light emitting display panel.

Abstract: An organic light-emitting display apparatus including a substrate; a pixel electrode on the substrate; a pixel-defining layer including an opening exposing at least a portion of the pixel electrode; an intermediate layer including a center area on the pixel electrode and a side area extending from the center area and arranged on the pixel-defining layer, the intermediate layer including one or more common layers and an emission layer; a protective layer covering top surfaces of the center area and the side area of the intermediate layer and exposing at least a portion of the pixel-defining layer; and an opposite electrode spaced apart from the intermediate layer by the protective layer and arranged on the protective layer and portions of the pixel-defining layer, the portions being exposed by the protective layer.

Abstract: Aspects include features for improving the reliability of a reflective base structure for light emitting diodes (LED) chip-on-board (COB) array products. The reflective base structure reduces reflective material of a reflective layer (e.g., silver) from migrating into adjacent layers. In one configuration used to reduce the migration of reflective material, a reflective base for a light-emitting diode (LED) may comprise a substrate, a reflective layer, and a diffusion barrier layer between the substrate and the reflective layer. In another configuration used to reduce the migration of reflective material, a reflective base for an LED comprising: a substrate, a reflective layer; and a planarizing layer between the substrate and the reflective layer, a thickness of the planarizing layer between the substrate and the reflective layer being less than 70 nm.

Abstract: To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.

Abstract: A photoelectric device includes a first electrode and a second electrode facing each other, a photoelectric conversion layer between the first electrode and the second electrode and including a light absorbing material configured to selectively absorb first visible light including one of visible light in a blue wavelength region of greater than or equal to about 380 nm and less than about 500 nm, visible light in a green wavelength region of about 500 nm to about 600 nm, and visible light in a red wavelength region of greater than about 600 nm and less than or equal to about 700 nm, and a plurality of nanostructures between the first electrode and the photoelectric conversion layer and configured to selectively reflect the first visible light.

Abstract: A bonding wire for a semiconductor device, which is suitable for on-vehicle devices bonding wire, has excellent capillary wear resistance and surface flaw resistance while ensuring high bonding reliability and further satisfies overall performance including ball formability and wedge bondability, the bonding wire including: a Cu alloy core material; a Pd coating layer formed on a surface of the Cu alloy core material; and a Cu surface layer formed on a surface of the Pd coating layer, in which the bonding wire for semiconductor device contains Ni, a concentration of the Ni in the bonding wire is 0.1 to 1.2 wt. %, the Pd coating layer is 0.015 to 0.150 ?m in thickness, and the Cu surface layer is 0.0005 to 0.0070 ?m in thickness.

Abstract: A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.