Patents Examined by Eugene Lee
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Patent number: 11296018Abstract: A display device includes: a substrate; a pixel connected to a gate line and a data line on the substrate; a connection unit connected to one of the gate line and the data line of the substrate; and a driving integrated circuit mounted on the connection unit. The connection unit includes: a lead line connected to the driving integrated circuit; and a first dummy line adjacent to a first side of the connection unit, the first side intersecting a side of the substrate, the first side extending in a first direction, the first dummy line extending in a second direction intersecting the first direction. The side of the substrate overlaps the connection unit, and a third side of the connection unit overlaps the substrate without intersecting the side of the substrate, the third side extending in the second direction. The first dummy line is disposed between the side of the substrate and the third side of the connection unit.Type: GrantFiled: July 14, 2020Date of Patent: April 5, 2022Assignee: Samsung Display Co., Ltd.Inventor: Myongsoo Oh
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Patent number: 11282992Abstract: A light-emitting module includes: a semiconductor light-emitting element which emits deep ultraviolet light; a liquid sealing the semiconductor light-emitting element; and a package for accommodating the semiconductor light-emitting element and the liquid. The liquid is transparent to the deep ultraviolet light. The package has a transparent member transparent to the deep ultraviolet light. For that reason, a highly reliable light-emitting module provided with the semiconductor light-emitting element that emits the deep ultraviolet light can be provided.Type: GrantFiled: November 22, 2016Date of Patent: March 22, 2022Assignee: NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGYInventors: Shinichiro Inoue, Manabu Taniguchi, Kosei Nakaya
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Patent number: 11282716Abstract: A method of forming a planarized integration structure is provided. The method includes forming at least two conductive pillars on a packaging substrate, wherein the packaging substrate has a positive or convex meniscus shape. The method further includes placing a bridging die on the packaging substrate between an adjacent pair of the at least two conductive pillars, wherein the bridging die includes one or more conductive interconnects. The method further includes forming a cover layer on the substrate over the at least two conductive pillars and the bridging die, and planarizing the conductive pillars and the one or more conductive interconnects.Type: GrantFiled: November 8, 2019Date of Patent: March 22, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta Ghate Farooq, James Kelly
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Patent number: 11276801Abstract: A light-emitting element includes: a semiconductor stacked body; an insulating film located on a p-type semiconductor layer; a p-side electrode located on the insulating film, the p-side electrode comprising a pad portion and an extension portion, the extension portion being continuous with the pad portion in a first direction; a light-transmissive conductive film located on the p-type semiconductor layer and on the insulating film, the light-transmissive conductive film having an opening that is continuous along the extension portion on the insulating film; and a reflective film located between the insulating film and the p-side electrode in the opening. The opening includes a first opening and a second opening. In the second direction, the light-transmissive conductive film is electrically connected to the extension portion of the p-side electrode at a portion adjacent to a region where the first opening is located.Type: GrantFiled: March 4, 2020Date of Patent: March 15, 2022Assignee: NICHIA CORPORATIONInventor: Shun Kitahama
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Patent number: 11270951Abstract: A substrate that includes at least one dielectric layer, a first inductor formed in the at least one dielectric layer, a second inductor formed in the at least one dielectric layer, and a patterned ground layer formed on a metal layer of the substrate. The patterned ground layer is configured to provide electromagnetic (EM) shielding. The patterned ground layer includes a plurality of slots. The plurality of slots may be filled with the at least one dielectric layer. The plurality of slots may include a slot with a rectangular shape, a slot with a polygon shape, a slot with a circular shape, or combinations thereof. The patterned ground layer may include at least one slot that, individually or collectively, has a shape of a spiral.Type: GrantFiled: December 13, 2018Date of Patent: March 8, 2022Assignee: QUALCOMM IncorporatedInventors: Rui Tang, Zhongning Liu, Chenqian Gan
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Patent number: 11244787Abstract: A capacitor includes: a plurality of bottom electrodes; a dielectric layer formed over the bottom electrodes; and a top electrode formed over the dielectric layer, wherein the top electrode includes a carbon-containing material and a germanium-containing material that fill a gap between the bottom electrodes.Type: GrantFiled: November 8, 2019Date of Patent: February 8, 2022Assignee: SK hynix Inc.Inventor: Seung-Muk Kim
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Patent number: 11215647Abstract: A SiC semiconductor device is provided that is capable of improving the detection accuracy of the current value of a principal current detected by a current sensing portion by restraining heat from escaping from the current sensing portion to a wiring member joined to a sensing-side surface electrode. The semiconductor device 1 includes a SiC semiconductor substrate, a source portion 27 including a principal-current-side unit cell 34, a current sensing portion 26 including a sensing-side unit cell 40, a source-side surface electrode 5 disposed above the source portion 27, and a sensing-side surface electrode 6 that is disposed above the current sensing portion 26 and that has a sensing-side pad 15 to which a sensing-side wire is joined, and, in the semiconductor device 1, the sensing-side unit cell 40 is disposed so as to avoid being positioned directly under the sensing-side pad 15.Type: GrantFiled: June 3, 2020Date of Patent: January 4, 2022Assignee: ROHM CO., LTD.Inventor: Katsuhisa Nagao
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Patent number: 11217481Abstract: A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.Type: GrantFiled: November 8, 2019Date of Patent: January 4, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicholas Anthony Lanzillo, Koichi Motoyama, Somnath Ghosh, Christopher J. Penny, Robert Robison, Lawrence A. Clevenger
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Patent number: 11205725Abstract: The present disclosure provides a buffer structure, a display panel, and a manufacturing method of the buffer structure. The display panel comprises at least one of the buffer structures. The buffer structure comprises a first inorganic layer, a second inorganic layer, and an organic layer. Trapezoidal grooves are disposed at intervals on one side surface of the first inorganic layer; the second inorganic layer is disposed on one side surface having the trapezoidal grooves of the first inorganic layer, covers inside surfaces of the trapezoidal grooves, is connected at openings of the trapezoidal grooves, and forms capillary channels; and the organic layer is filled inside the capillary channels.Type: GrantFiled: November 4, 2019Date of Patent: December 21, 2021Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.Inventor: Kun Wang
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Patent number: 11196015Abstract: A display apparatus and a manufacturing method of the display apparatus are provided. The display apparatus includes a substrate and a first sub-pixel located on the substrate. The first sub-pixel includes a first bottom electrode, a first light-emitting layer, and a first top electrode. The first light-emitting layer is located on the first bottom electrode. The first light-emitting layer includes a first groove structure or a first protrusion structure. The first top electrode is located on the first light-emitting layer.Type: GrantFiled: November 4, 2019Date of Patent: December 7, 2021Assignee: Au Optronics CorporationInventors: Shang-Ta Tsai, Yi-Hwa Song, Hsien-Hung Chen, Hsi-An Chen
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Patent number: 11195896Abstract: An organic light emitting diode display includes a substrate, a semiconductor layer on the substrate, the semiconductor layer including a doped area and an undoped area, a first insulation layer that covers the semiconductor layer, a first conductor on the first insulation layer, a second insulation layer that covers the first conductor, a second conductor on the second insulation layer, a third insulation layer that covers the second conductor, and a third conductor on the third insulation layer, wherein, in the semiconductor layer that overlaps the first conductor, the doped area is between undoped areas.Type: GrantFiled: June 6, 2019Date of Patent: December 7, 2021Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Sung Hwan Kim, Won Kyu Kwak, Sang Moo Choi, Ji-Hyun Ka, Chul Kyu Kang, Dong Wook Kim, Won Se Lee
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Patent number: 11189645Abstract: There is provided a high-definition active matrix substrate while suppressing an occurrence of pixel defects. The active matrix substrate includes a first semiconductor film corresponding to one of two sub-pixels adjacent to each other in a row direction, a second semiconductor film corresponding to the other of two sub-pixels, a transistor using part of the first semiconductor film as a channel in the row direction, and a pixel electrode connected to a drain electrode of the transistor through a contact hole. In a plan view, a distance (dc) in the row direction from a drain electrode-side edge of the channel to a bottom surface of the contact hole is 0.15 or more times a sub-pixel pitch (dp) in the row direction.Type: GrantFiled: March 26, 2018Date of Patent: November 30, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Tetsuo Kikuchi, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Patent number: 11188843Abstract: A quantum computing device includes multiple co-planar waveguide flux qubits, at least one coupler element arranged such that each co-planar waveguide flux qubit, of the multiple co-planar waveguide flux qubits, is operatively couplable to each other co-planar waveguide flux qubit, of the multiple co-planar waveguide flux qubits, of the quantum computing device, and a tuning quantum device, in which the tuning quantum device is in electrical contact with a first co-planar waveguide flux qubit of the plurality of co-planar waveguide flux qubits and with a second co-planar waveguide flux qubit of the plurality of co-planar waveguide flux qubits.Type: GrantFiled: April 24, 2020Date of Patent: November 30, 2021Assignee: Google LLCInventors: Alireza Shabani Barzegar, Pedram Roushan, Yu Chen, Hartmut Neven
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Patent number: 11171016Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.Type: GrantFiled: June 4, 2020Date of Patent: November 9, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Feng Chen, Chih-Hua Chen, Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo, Hui-Jung Tsai, Hao-Yi Tsai
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Patent number: 11164852Abstract: A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a semiconductor device over the redistribution structure, removing a portion of the dielectric layer to form an opening to expose the UBM layer, and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer.Type: GrantFiled: February 11, 2019Date of Patent: November 2, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jing-Cheng Lin, Po-Hao Tsai
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Patent number: 11152595Abstract: A method for manufacturing a display device including providing a protection resin having a base resin, a first initiator, and a second initiator to the non-display area, irradiating light having a first wavelength region to the protection resin to form a preliminary protection layer, bending the flexible substrate so that the bending part has a first curvature radius, and additionally curing the preliminary protection layer to form a protection layer.Type: GrantFiled: January 11, 2019Date of Patent: October 19, 2021Assignee: Samsung Display Co., Ltd.Inventors: Myoung-ha Jeon, Jinho Kim, Hyeonjeong Oh, Kichang Lee
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Patent number: 11133451Abstract: A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.Type: GrantFiled: August 30, 2019Date of Patent: September 28, 2021Assignee: Google LLCInventors: Joshua Yousouf Mutus, Erik Anthony Lucero
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Patent number: 11133450Abstract: A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.Type: GrantFiled: August 30, 2019Date of Patent: September 28, 2021Assignee: Google LLCInventors: Joshua Yousouf Mutus, Erik Anthony Lucero
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Patent number: 11127733Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layType: GrantFiled: February 6, 2020Date of Patent: September 21, 2021Assignee: Infineon Technologies AGInventors: Andre Schmenn, Stefan Pompl, Damian Sojka, Katharina Umminger
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Patent number: 11121224Abstract: An integrated circuit (IC) includes a field-plated transistor including a substrate having a semiconductor surface layer, at least one body region in the semiconductor surface layer, and at least a first trench isolation region adjacent to the body region having at least a first tapered sidewall that has an average angle along its full length of 15 to 70 degrees. A gate is over the body region. A field plate is over the first tapered trench isolation region. A source is on one side of the field plate and a drain is on an opposite side of the field plate. The IC also includes circuitry for realizing at least one circuit function having a plurality of transistors which are configured together with the field-plated transistor that utilize second trench isolation regions for isolation that have an average angle of 75 and 90 degrees.Type: GrantFiled: February 8, 2019Date of Patent: September 14, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ming-Yeh Chuang, Elizabeth Costner Stewart