Abstract: Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment.

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.

Abstract: A method of forming a semiconductor device includes providing a heterojunction semiconductor body. The heterojunction semiconductor body includes a type III-V semiconductor back-barrier region, a type III-V semiconductor channel layer formed on the back-barrier region, and a type III-V semiconductor barrier layer formed on the back-barrier region. A first two-dimensional charge carrier gas is at an interface between the channel and barrier layers. A second two-dimensional charge carrier gas is disposed below the first two-dimensional charge carrier gas. A deep contact structure in the heterojunction semiconductor body that extends through the channel layer and forms an interface with the second two-dimensional charge carrier gas is formed. The first semiconductor region includes a first contact material that provides a conductive path for majority carriers of the second two-dimensional charge carrier gas at the interface with the second two-dimensional charge carrier gas.

Abstract: A semiconductor device with reduce capacitance coupling effect which can reduce the overall parasitic capacitances is disclosed. The semiconductor device includes a gate sidewall spacer with a negative capacitance dielectric layer with and without a dielectric layer. The semiconductor device may also include a plurality of interlevel dielectric (ILD) with a layer of negative capacitance dielectric layer followed by a dielectric layer disposed in-between metal lines in any ILD and combinations. The negative capacitance dielectric layer includes a ferroelectric material which has calculated and selected thicknesses with desired negative capacitance to provide optimal total overlap capacitance in the circuit component which aims to reduce the overall capacitance coupling effect.

Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.

Abstract: A method of processing an engineered substrate structure includes providing an engineered substrate structure including a polycrystalline substrate and an engineered layer encapsulating the polycrystalline substrate, forming a sacrificial layer coupled to the engineered layer, joining a solid state device structure to the sacrificial layer, forming one or more channels in the solid state device structure by removing one or more portions of the solid state device structure to expose one or more portions of the sacrificial layer, flowing an etching chemical through the one or more channels to the one or more exposed portions of the sacrificial layer, and dissolving the sacrificial layer by interaction between the etching chemical and the sacrificial layer, thereby separating the engineered substrate structure from the solid state device structure.

Abstract: The film forming apparatus includes a reaction chamber in which a substrate subjected to film forming processing can be placed, a gas supplier provided in an upper part of the reaction chamber, having a portion where gas is introduced and gas supply holes to face the substrate, a source-gas introducing line introducing a source gas into the gas supplier, a replacement-gas introducing line introducing a replacement gas into the gas supplier, a discharge line discharging the replacement gas along with a remaining source gas which is the source gas remaining in the gas supplier from the gas supplier; and a controller controlling one of an introduction amount of the replacement gas and a discharge amount of the remaining source gas and the replacement gas to be an amount corresponding to the other amount.

Abstract: A magnetic memory according to an embodiment includes: first to third terminals; a nonmagnetic conductive layer including first to third regions, the second region being disposed between the first and third regions, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; and a magnetoresistive element disposed to correspond to the second region, including a first magnetic layer electrically connected to the third terminal, a second magnetic layer disposed between the first magnetic layer and the second region, and a nonmagnetic layer disposed between the first and second magnetic layers, the conductive layer including at least one of an alloy including Ir and Ta, an alloy including Ir and V, an alloy including Au and V, an alloy including Au and Nb, or an alloy including Pt and V, each of the alloys having an fcc structure.

Abstract: A method of processing a target object is provided. In the method, the target object including a first protrusion portion, a second protrusion portion, an etching target layer and a groove portion, the etching target layer having a region belonging to the first protrusion portion and a region belonging to the second protrusion portion, the groove portion being provided on a main surface of the target object, being provided on the etching target layer and being defined by the first protrusion portion and the second protrusion portion, and an inner surface of the groove portion being included in the main surface of the target object is prepared, and a first sequence is repeatedly performed N times (N is an integer equal to or larger than 2). The first sequence includes (a) forming a protection film conformally on the main surface; and (b) etching a bottom portion of the groove portion with plasma of a gas generated after the process a is performed.

Abstract: An optical module comprising: a plurality of active optoelectronic components each one mounted on a respective printed circuit board (PCB), wherein each active optoelectronic component is associated with a respective different optical channel; a plurality of optical assemblies, each one is substantially aligned over a different respective optical channel; and a spacer separating the active optoelectronic components and PCBs from the optical assemblies, wherein the optical assemblies are attached by adhesive directly to an optical assembly-side surface of the spacer. A first active optoelectronic component is separated, by the spacer, from a first optical assembly by a first distance and a second active optoelectronic component is separated, by the spacer, from a second optical assembly by a different second distance.

Abstract: Methods for forming a metallic film on a substrate by cyclical deposition are provided. In some embodiments methods may include contacting the substrate with a first reactant comprising a non-halogen containing metal precursor comprising at least one of copper, nickel or cobalt and contacting the substrate with a second reactant comprising a hydrocarbon substituted hydrazine. In some embodiments related semiconductor device structures may include at least a portion of a metallic interconnect formed by cyclical deposition processes.

Abstract: Methods for forming a metallic film on a substrate by cyclical deposition are provided. In some embodiments methods may include contacting the substrate with a first reactant comprising a non-halogen containing metal precursor comprising at least one of copper, nickel or cobalt and contacting the substrate with a second reactant comprising a hydrocarbon substituted hydrazine. In some embodiments related semiconductor device structures may include at least a portion of a metallic interconnect formed by cyclical deposition processes.

Abstract: Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate including a plurality of build-up layers, such as bumpless build-up layer (BBUL). In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.

Abstract: The present application discloses a thin film transistor including a base substrate; an active layer; and a first linear polarization block configured to shield at least a portion of the active layer from light. A projection of the first linear polarization block on the base substrate at least partially overlaps with that of the active layer.

Abstract: A display device includes a substrate which includes a display area and a non-display area, a pixel unit which is provided in the display area and includes a plurality of pixel columns, and data lines which are respectively connected to the pixel columns and apply data signals to the pixel columns. The non-display area includes a fanout area, a bent area, and a pad area which are sequentially arranged. The respective data lines are disposed on different layers in the fanout area and the pad area. A resulting display device can reduce resistance deviation between data signals in a first data line and a second data line, thereby reducing vertical line defects.

Abstract: The present application discloses a liquid crystal array substrate having an array of a plurality of subpixel areas. The liquid crystal array substrate includes a plurality of first signal lines and a plurality of second signal lines crossing over each other; and a plurality of pixel electrodes corresponding to the plurality of subpixel areas, each of the plurality of subpixel areas including a single one of the plurality of pixel electrodes, and the single one of the plurality of pixel electrodes in each of the plurality of subpixel areas being an integral pixel electrode. Each of the plurality of subpixel areas includes a first subarea and a second subarea having a substantially mirror symmetry with respect to a plane of mirror symmetry containing the one of the plurality of second signal lines in plan view of the array of the plurality of subpixel areas. The first subarea and the second subarea constitute an integral subpixel area.

Abstract: A touch substrate manufactured by three-dimensional printing and a method for manufacturing the same are disclosed. The method for manufacturing the touch substrate works together with a three-dimensional printer. The three-dimensional printer includes a first nozzle, a second nozzle, and a light source. The method includes the steps of: jetting a photocuring material by the first nozzle and exposing the photocuring material to the light source to form a base layer; jetting a conductive material on the base layer by the second nozzle and exposing the conductive material to the light source to form a touch electrode layer; and jetting the photocuring material on the base layer and the touch electrode layer by the first nozzle and exposing the photocuring material to the light source to form a protective layer. The touch electrode layer is embedded between the base layer and the protective layer.

Abstract: A semiconductor device includes a substrate, a first wiring line, a semiconductor film, a second wiring line, and an insulating film. The substrate includes first, second, and third regions provided adjacently in this order in a predetermined direction. The first wiring line is provided on the substrate and provided in each of the first, second, and third regions. The semiconductor film has a low-resistance region in at least a portion thereof. The semiconductor film is provided between the first wiring line and the substrate in the first region, and is in contact with the first wiring line in the second region. The second wiring line is provided at a position closer to the substrate than the semiconductor film, and is in contact with the first wiring line in the third region. The insulating film is provided between the first wiring line and the semiconductor film in the first region.

Abstract: Techniques for forming VFETs having different gate lengths (and optionally different gate pitch and/or gate oxide thickness) on the same wafer are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a wafer including a first fin(s) patterned to a first depth and a second fin(s) patterned to a second depth, wherein the second depth is greater than the first depth; forming bottom source/drains at a base of the fins; forming bottom spacers on the bottom source/drains; forming gates alongside the fins, wherein the gates formed alongside the first fin(s) have a first gate length Lg1, wherein the gates formed alongside the second fin(s) have a second gate length Lg2, and wherein Lg1<Lg2; forming top spacers over the gates; and forming top source/drains over the top spacers. A VFET is also provided.

Abstract: An apparatus for conveying a substrate includes a base along which the substrate is conveyed, a first upward gas ejecting section, a second upward gas ejecting section and a third upward gas ejecting section disposed over the base, the third upward gas ejecting section being disposed between the first and second upward gas ejecting sections, and a first downward gas ejecting section and a second downward gas ejecting section disposed above and facing respective portions of the third upward gas ejecting section. Gas ejected upward from the first, second and third upward gas ejecting sections floats the substrate. The substrate is subjected to pressure by gas ejected downward from the first and second downward gas ejecting sections. The first and second downward gas ejecting sections are spaced to provide a working area therebetween and through which the substrate is irradiated with a laser beam.