Abstract: Systems and methods for releasing semiconductor dies during pick and place operations are disclosed. In one embodiment, a system for handling semiconductor dies comprises a support member positioned to carry at least one semiconductor die releasably attached to a support substrate. The system further includes a picking device having a pick head coupleable to a vacuum source and positioned to releasably attach to the semiconductor die at a pick station. The system still further includes a cooling member coupleable to a cold fluid source and configured to direct a cold fluid supplied by the cold fluid source toward the support substrate at the pick station. The cold fluid cools a die attach region of the substrate where the semiconductor die is attached to the substrate to facilitate removal of the semiconductor die.

Abstract: A light emitting diode assembly comprising such thermal management assembly is shown and described herein. The light emitting diode assembly may comprise a light emitting diode in thermal contact with a heat spreader. The heat spreader may comprise a core and/or fins. The core and/or fins comprise a thermal pyrolytic graphite material. The thermal management assembly comprising the core and/or fins can dissipate heat from the light emitting diode.

Abstract: A method of manufacturing electronic dies by separating a wafer into electronic dies, wherein the method comprises forming a groove in the wafer with a first material removal tool having a first thickness, enlarging the groove by a second material removal tool having a second thickness larger than the first thickness, and subsequently increasing a depth of the groove by a third material removal tool having a third thickness smaller than the second thickness until the wafer is separated.

Abstract: A method of processing a plate-shaped workpiece that includes on a reverse side thereof a layered body containing metal which is formed in superposed relation to projected dicing lines includes the steps of holding the reverse side of the workpiece on a holding table, thereafter, applying a laser beam having a wavelength that is absorbable by the workpiece to a face side thereof along the projected dicing lines to form laser-processed grooves in the workpiece which terminate short of the layered body, and thereafter, cutting bottoms of the laser-processed grooves with a cutting blade to sever the workpiece together with the layered body along the projected dicing lines. The step of cutting bottoms of the laser-processed grooves includes the step of cutting bottoms of the laser-processed grooves while supplying a cutting fluid containing an organic acid and an oxidizing agent to the workpiece.

Abstract: A method of forming a plurality of semiconductor devices includes applying a tape material to a back side of a semiconductor device having a silicon layer on the back side and a circuitry layer on the front side, lasing with an infrared laser the silicon layer through the tape material, lasing with a second laser the circuitry layer, and expanding the tape material for form a plurality of semiconductor devices. The second layer may be an ultraviolet laser. The lasers may be irradiated in a pattern on the bottom side and the top side. The second layer may form a groove in the circuitry layer that does not penetrate the silicon layer. The infrared laser may cleave a portion of the silicon lattice of the silicon layer. A coating may be applied to the circuitry layer prior to being irradiated with the second laser.

Abstract: A semiconductor device with reduce capacitance coupling effect which can reduce the overall parasitic capacitances is disclosed. The semiconductor device includes a gate sidewall spacer with a negative capacitance dielectric layer with and without a dielectric layer. The semiconductor device may also include a plurality of interlevel dielectric (ILD) with a layer of negative capacitance dielectric layer followed by a dielectric layer disposed in-between metal lines in any ILD and combinations. The negative capacitance dielectric layer includes a ferroelectric material which has calculated and selected thicknesses with desired negative capacitance to provide optimal total overlap capacitance in the circuit component which aims to reduce the overall capacitance coupling effect.

Abstract: A method of forming a semiconductor structure comprises forming a plurality of fins disposed over a top surface of a substrate and forming one or more vertical transport field-effect transistors (VTFETs) from the plurality of fins using a replacement metal gate (RMG) process. A gate surrounding at least one fin of a given one of the VTFETs comprises a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin.

Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

Abstract: Disclosed are an organic light-emitting display device and a method of manufacturing the same. In the organic light-emitting display device, a first protrusion is provided to protrude from a planarization layer, which has a pixel contact hole configured to expose a thin-film transistor disposed on a substrate, toward a cathode electrode of an organic light-emitting element, and a side surface angle of the first protrusion differs from a side surface angle of the planarization layer, which is exposed through the pixel contact hole. Thereby, the cathode electrode and an auxiliary connection electrode may be electrically connected to each other without a separate partition, which may simplify the structure and the manufacturing process of the organic light-emitting display device.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.

Abstract: A cell test method used for a fanout zone of a step location of a liquid crystal displays panel or an organic light emitting display panel, comprising the following steps: adding a cell test pad on an edge of a semi-finished flexible printed circuit board on glass (FOG) for the cell test method if length of the edge of the semi-finished FOG is greater than a critical value; placing alignment marks on the cell test pad; aligning the cell test pad by using the charge-coupled device; multiplexing process of some pins of the flexible printed circuit board to send signals for a cell test if the length of an edge of the semi-finished FOG is less than the critical value, controlling the signals to turn on by a metal oxide semiconductor.

Abstract: All-printed paper-based substrate memory devices are described. In an embodiment, a paper-based memory device is prepared by coating one or more areas of a paper substrate with a conductor material such as a carbon paste, to form a first electrode of a memory, depositing a layer of insulator material, such as titanium dioxide, over one or more areas of the conductor material, and depositing a layer of metal over one or more areas of the insulator material to form a second electrode of the memory. In an embodiment, the device can further include diodes printed between the insulator material and the second electrode, and the first electrode and the second electrodes can be formed as a crossbar structure to provide a WORM memory. The various layers and the diodes can be printed onto the paper substrate by, for example, an ink jet printer.

Abstract: A deposition method relating to semiconductor technology is presented. The deposition method includes: conducting a first deposition in a reaction chamber at a first deposition temperature; conducting a cool-down process on the reaction chamber, and conducting a second deposition during the cool-down process. In the first deposition, the thin-films deposited on the periphery of a wafer are thicker than those deposited on the center of a wafer, while in the second deposition, the thin-films deposited on the periphery of a wafer are thinner that those deposited on the center of a wafer. Therefore the thin-films deposited by this deposition method are more homogeneous in thickness that those deposited with conventional methods.

Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.

Abstract: The present disclosure relates generally to techniques for forming a continuous adhesion layer for a contact plug. A method includes forming an opening through a dielectric layer to an active area on a substrate. The method includes performing a first plasma treatment along a sidewall of the opening. The method includes performing an atomic layer deposition (ALD) process to form a metal nitride layer along the sidewall of the opening. The ALD process includes a plurality of cycles. Each cycle includes flowing a precursor to form a metal monolayer along the sidewall and performing a second plasma treatment to treat the metal monolayer with nitrogen. The method includes depositing a conductive material on the metal nitride layer in the opening to form a conductive feature.

Abstract: A method for manufacturing a micro light emitting diode device is provided. A connection layer and epitaxial structures are formed on a substrate. A first pad is formed on each of the epitaxial structures. A first adhesive layer is formed on the connection layer, and the first adhesive layer encapsulates the epitaxial structures and the first pads. A first substrate is connected to the first adhesive layer. The substrate is removed, and a second substrate is connected to the connection layer through a second adhesive layer. The first substrate and the first adhesive layer are removed. The connection layer located between any two adjacent epitaxial structures are partially removed to form a plurality of connection portions. Each of the connection portions is connected to the corresponding epitaxial structure, and a side edge of each of the connection portions protrudes from a side wall surface of the corresponding epitaxial structure.

Abstract: An evaporation method and an evaporation device for an organic light-emitting diode substrate are proposed. The evaporation method includes: step 1, regulating a distance between a supporting module for supporting a substrate and a crucible platform of an evaporation device; step 2, adjusting a direction of opening of a crucible disposed on the crucible platform; and step 3, placing a substrate to be evaporated on the supporting module and volatizing an evaporation source in the crucible and attaching the volatized evaporation source onto a surface of the substrate.

Abstract: A chip scale package (CSP) structure for an image sensor comprises an image sensor chip, wherein the image sensor chip comprises a semiconductor substrate having a top surface to receive light, a plurality of color filters disposed over the top surface, and a plurality of micro lenses disposed on the plurality of color filters. A low refractive index material is disposed over the image sensor chip, wherein the low refractive index material covers the plurality of micro lenses, and wherein a refractive index of the low refractive index material is lower than a refractive index of the plurality of micro lenses. A cover glass is disposed directly on the low refractive index material, wherein no air gap is between the cover glass and the low refractive index material, and between the low refractive index material and the image sensor chip. Therefore, the cover glass is fully supported by the low refractive index material without any dams.

Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

Abstract: A semiconductor device can include a first metal trace, a first via disposed on the first metal trace, a second metal trace disposed on the first via, and an insulator interposed between the first metal trace and the first via. The insulator can be configured to lower an energy barrier or redistribute structure defects or charge carriers, such that the first metal trace and the first via are electrically connected to each other when power is applied. The semiconductor device can further include a dummy via disposed on the first metal trace.