Abstract: A method of forming logic cell contacts, forming CMOS integrated circuit (IC) chips including the FETs and the IC chips. After forming replacement metal gates (RMG) on fin field effect transistor (finFET) pairs, gates are cut on selected pairs, separating PFET gates from NFET gates. An insulating plug formed between the cut gates isolates the pairs of cut gates from each other. Etching offset gate contacts at the plugs partially exposes each plug and one end of a gate sidewall at each cut gate. A second etch partially exposes cut gates. Filling the open offset contacts with conductive material, e.g., metal forms sidewall cut gate contacts and stitches said cut gate pairs together.

Abstract: A semiconductor structure includes a substrate and a fin. The fin extends from the substrate and is formed with a hole therethrough. The hole is defined by a confronting pair of wall parts. One of the wall parts is more arcuate than the other of the wall parts. A method for fabricating the semiconductor structure is also disclosed.

Abstract: A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.

Abstract: A data acquisition system coupled to a mains power source and a method of operating the data acquisition system are disclosed. A test probe is configured to be coupled to a subject, and an analog to digital converter converts a signal from the test probe to samples. A noise replica generator generates estimates of noise in the samples, and a noise removal block removes from each sample an estimate of noise therein. When the subject is undergoing stimulation, the samples are provided to only the noise removal block. When the subject is not undergoing stimulation, the samples are provided to both the noise replica generator and the noise removal block.

Abstract: The present disclosure provides a test element group, an array substrate, a test device and a test method. The test element group includes an array of Thin Film Transistors (TFTs), in which first electrodes of the TFTs in each row are connected to a first connection end, second electrodes of the TFTs in each column are connected to a second connection end, and third electrodes of all of the TFTs in the array are connected to an identical third connection end. The first electrode, the second electrode and the third electrode correspond to the source electrode, the drain source and the gate source of the TFT.

Abstract: A method includes forming a hard mask over a base material, and forming an I-shaped first opening in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material.

Abstract: Apparatus for measuring light scattering of a sample comprising a light beam source, means for collimating the beam and making it impinge on the sample in a perpendicular direction, at least one light sensor, and at least one spatial filter between the sample and the optical sensor, provided with two apertures, means for measuring the total power reaching the sensor and means for measuring the power of beams with a low k vector after the beam traverses the filter. The invention provides thus a simplified, portable and compact device for measuring different parameters like haze, turbidity, etc. can be built, for any sample and without the need of changing detectors.

Abstract: Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a word line cell over a substrate and forming a dielectric layer over the word line cell. The method further includes forming a conductive layer over the dielectric layer and polishing the conductive layer until the dielectric layer is exposed. The method further includes forming an oxide layer on a top surface of the conductive layer and removing portions of the conductive layer not covered by the oxide layer to form a memory gate.

Abstract: Provided are a surface-modified metal oxide particle dispersion liquid and the like including surface-modified metal oxide particles that are dispersed in a dispersion medium, the surface-modified metal oxide particles being obtained by modifying surfaces of metal oxide particles to have hydrosilyl groups, hydrophobic functional groups, and silanol groups. In the surface-modified metal oxide particle dispersion liquid, a ratio of the hydrosilyl groups to the silanol groups is 5:95 or higher and 50:50 or lower.

Abstract: Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

Abstract: A semiconductor device includes a substrate, a first semiconductor layer formed over the substrate, a plurality of contact layers formed over portions of the first semiconductor layer, a second semiconductor layer formed over another portion of the first semiconductor layer and on side surfaces of the contact layers, a source electrode formed on one of the contact layers, a drain electrode formed on another one of the contact layers, and a gate electrode formed on the second semiconductor layer. The first semiconductor layer is formed of a material including GaN, the second semiconductor layer is formed of Inx1Aly1Ga1-x1-y1N (0<x1?0.2, 0<y1<1), and the contact layers are formed of a material including GaN.

Abstract: A semiconductor device, including: a first memory cell including a first transistor; a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor self-aligned to the first transistor; and a plurality of junctionless transistors, where at least one of the junctionless transistors controls access to at least one of the memory cells.

Abstract: An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material based buffer layer on the first III-V material based buffer layer, the second III-V material including aluminum; and a III-V material based device channel layer on the second III-V material based buffer layer. Another embodiment includes the above subject matter and the first and second III-V material based buffer layers each have a lattice parameter equal to the III-V material based device channel layer. Other embodiments are included herein.

Abstract: An array substrate, a display apparatus applying the same and the assembly method thereof are provided, wherein the array substrate includes a substrate having a plurality of pixels, each of the pixels at least includes a thin film transistor (TFT) device, a first electrode, a second electrode separated from the first electrode all of which are disposed on the substrate. at least one of the first electrode and the second electrode is electrically contacted to the TFT device, and either the first electrode or the second electrode has a magnetic force generator used to generate a magnetic force substantially ranging from 10 gauss to 1000 gauss.

Abstract: A semiconductor device includes a semiconductor substrate, a radiation-sensing region, at least one isolation structure, and a doped passivation layer. The radiation-sensing region is present in the semiconductor substrate. The isolation structure is present in the semiconductor substrate and adjacent to the radiation-sensing region. The doped passivation layer at least partially surrounds the isolation structure in a substantially conformal manner.

Abstract: Microelectronic devices including an electromagnetic shield over a desired portion of a substrate. The magnetic shield is formed of conductive particles within a selectively curable layer, such as a solder resist material. After application to the substrate, the conductive particles are allowed to settle to form a conductive structure to serve as an electromagnetic shield. The electromagnetic shield can be formed primarily over regions of the substrate containing conductive traces coupled in the package to communicate signals presenting a risk of causing electromagnetic interference with other devices.

Abstract: A stack for a semiconductor device and a method for making the stack are disclosed. The stack includes a plurality of sacrificial layers in which each sacrificial layer has a first lattice parameter; and at least one channel layer that has a second lattice parameter in which the first lattice parameter is less than or equal to the second lattice parameter, and each channel layer is disposed between and in contact with two sacrificial layers and includes a compressive strain or a neutral strain based on a difference between the first lattice parameter and the second lattice parameter.

Abstract: A method of integrating a silicon-oxide-nitride-oxide-silicon (SONOS) transistor into a complementary metal-oxide-silicon (CMOS) baseline process. The method includes the steps of forming the gate oxide layer of at least one metal-oxide-silicon (MOS) transistor prior to forming a non-volatile (NV) gate stack of the SONOS transistor.

Abstract: A metal oxide thin film transistor and a preparation method thereof, as well as an array substrate, wherein the metal oxide thin film transistor comprises a base substrate, an active layer and a source-drain metal layer formed on the base substrate that contact each other and are located in different layers, the source-drain metal layer comprising separated source electrode and drain electrode; the active layer having a hollow structure in a channel area located between the source electrode and the drain electrode.

Abstract: A conductive pattern formation method of the present invention includes a first exposure step of radiating active light in a patterned manner to a photosensitive layer including a photosensitive resin layer provided on a substrate and a conductive film provided on a surface of the photosensitive resin layer on a side opposite to the substrate; a second exposure step of radiating active light, in the presence of oxygen, to some or all of the portions of the photosensitive layer not exposed at least in the first exposure step; and a development step of developing the photosensitive layer to form a conductive pattern following the second exposure step.