Abstract: The invention discloses a display panel and a manufacturing method thereof, and the display panel comprises a first substrate and a second substrate disposing correspondingly to each other, a pixel array disposed between the first substrate and the second substrate and an electrode disposed on a first substrate surface near the second substrate, and a through hole is disposed correspondingly to the second substrate and the electrode to expose part of the electrode by passing through the through hole. By applying the above-described method, the invention can achieve embedding functional components within the display panel, furthermore save a disposing space, increase a screen portion of display panel, and then improve using experiences of users.

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

Abstract: A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts.

Abstract: An electron emission device includes a substrate and an electron emission layer. The electron emission layer is provided above the substrate, and is provided with an opening. The electron emission layer has an edge defining the opening and is configured to emit electrons from the edge when the edge is irradiated with light.

Abstract: The metal thin film production method of the present invention includes, in the following order, the steps of: preparing a substrate (1) having thereon an underlayer (2) formed of an insulating resin; subjecting a surface of the underlayer (2) to a physical surface treatment for breaking bonds of organic molecules constituting the insulating resin; subjecting the substrate (1) to a heat treatment at a temperature of 200° C. or lower; applying a metal nanoparticle ink to the underlayer (2); and sintering metal nanoparticles contained in the metal nanoparticle ink at a temperature equal to or higher than a glass transition temperature of the underlayer (2). A fused layer (4) having a thickness of 100 nm or less is formed between the underlayer (2) and a metal thin film (3) formed by sintering the metal nanoparticles.

Abstract: An electronic device is provided to comprise a semiconductor memory unit that comprises: a substrate including active regions, which are extended in a second direction and disposed from each other in a first direction; a plurality of gates extended in the first direction and across with the active regions; a lower contact disposed in both sides of gates and coupling the active regions in the first direction; an upper contact of the lower contact overlapping with the active region out of the active regions in a side of each gate, and overlapping with the active regions in the other side of each gate; and first and second interconnection lines coupled to the upper contact, extended in the second direction, and being alternately disposed from each other in the first direction, wherein the upper contact of a side of the gates has a zigzag shape in a first oblique direction.

Abstract: An array substrate, a method for fabricating the array substrate, and a related display device are provided. The array substrate comprises: a base substrate with a plurality of first via holes; a plurality of first signal lines on a first side of the base substrate; and a plurality of first signal driver lines on a second side of the base substrate; wherein each first signal line is connected with at least one first signal driver line through at least one first via hole.

Abstract: Formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a low topography region and a high low topography region. The method also includes forming a first dielectric layer over the substrate. The method further includes forming a second dielectric layer over the stop layer. In addition, the method includes forming an opening in the first dielectric layer, the stop layer and the second dielectric layer. The method also includes forming a conductive material layer over the second dielectric layer. The conductive material layer fills the opening. The method further includes performing a polishing process over the conductive material layer until a top surface of the stop layer is exposed.

Abstract: A method provides a substrate having a top surface; forming a first semiconductor layer on the top surface, the first semiconductor layer having a first unit cell geometry; epitaxially depositing a layer of a metal-containing oxide on the first semiconductor layer, the layer of metal-containing oxide having a second unit cell geometry that differs from the first unit cell geometry; ion implanting the first semiconductor layer through the layer of metal-containing oxide; annealing the ion implanted first semiconductor layer; and forming a second semiconductor layer on the layer of metal-containing oxide, the second semiconductor layer having the first unit cell geometry. The layer of metal-containing oxide functions to inhibit propagation of misfit dislocations from the first semiconductor layer into the second semiconductor layer. A structure formed by the method is also disclosed.

Abstract: A semiconductor device includes: an n type semiconductor layer including an active region and an inactive region; an element structure formed in the active region and including at least an active side p type layer to form pn junction with n type portion of the n type semiconductor layer; an inactive side p type layer formed in the inactive region and forming pn junction with the n type portion of the n type semiconductor layer; a first electrode electrically connected to the active side p type layer in a front surface of the n type semiconductor layer; a second electrode electrically connected to the n type portion of the n type semiconductor layer in a rear surface of the n type semiconductor layer; and a crystal defect region formed in both the active region and the inactive region and having different depths in the active region and the inactive region.

Abstract: A semiconductor device includes a semiconductor substrate, and a dielectric layer on an upper surface of the semiconductor substrate. A contact stack is formed in the dielectric layer. The contact stack includes an electrically conductive contact element, and a contact liner on first and second opposing sidewalls of the contact element. A first air gap is interposed between the dielectric layer and the contact liner on the first side wall, and a second air gap interposed between the dielectric layer and the contact liner on the second side wall.

Abstract: A gaming system is disclosed which comprises a symbol selector arranged to select a plurality of symbols for display at a corresponding plurality of display positions, an outcome evaluator arranged to determine whether the selected symbols correspond to a winning symbol combination by evaluating symbols disposed in defined win lines, and a prize allocator arranged to allocate a prize to a player when a winning symbol combination exists in a defined win line. At least one display position is of different size to at least one other display position and the defined win lines are dependent on the respective sizes of and locations of the display positions. A corresponding method is also disclosed.

Abstract: Embodiments of the present invention provide an array substrate and a display device. The array substrate comprises a display area and a non-display area located in the periphery of the display area. A signal unit for transmitting external control signal and a gap region in which the signal unit is not disposed are provided in the non-display area. An auxiliary unit is disposed in the gap region, and the auxiliary unit and the signal unit have the same height and are electrically isolated from each other. A surface pattern of the signal unit is the same as that of the auxiliary unit in any corresponding part. In the array substrate, the segment difference in the non-display area due to the wiring are eliminated, and Rubbing Mura due to uneven rubbing strength of the rubbing roller on the periphery is reduced or eliminated, thereby achieving consistent rubbing effects.

Abstract: To provide a semiconductor device having improved performance. A method of manufacturing the semiconductor device includes forming, after formation of a control gate electrode and a memory gate electrode, a conductive film on an insulating film made of a high-dielectric-constant film via a metal film; patterning the conductive film and thereby forming a gate electrode including the metal film and the conductive film in a high-voltage MISFET region, while forming a metal film portion and a conductive film portion in a low-voltage MISFET region; and then, removing the conductive film portion from the low-voltage MISFET region, forming another conductive film on the metal film portion, and forming a gate electrode including the metal film portion and the another conductive film.

Abstract: The invention relates to Eu2+-activated phosphors, to a process of its preparation, the use of these phosphors in electronic and electro optical devices, such as light emitting diodes (LEDs) and solar cells and especially to illumination units comprising said magnesium alumosilicate-based phosphors.

Abstract: In an example, the present invention provides a gallium and nitrogen containing multilayered structure, and related method. The structure has a plurality of gallium and nitrogen containing semiconductor substrates, each of the gallium and nitrogen containing semiconductor substrates (“substrates”) having a plurality of epitaxially grown layers overlaying a top-side of each of the substrates. The structure has an orientation of a reference crystal direction for each of the substrates. The structure has a first handle substrate coupled to each of the substrates such that each of the substrates is aligned to a spatial region configured in a selected direction of the first handle substrate, which has a larger spatial region than a sum of a total backside region of plurality of the substrates to be arranged in a tiled configuration overlying the first handle substrate. The reference crystal direction for each of the substrates is parallel to the spatial region in the selected direction within 10 degrees or less.

Abstract: A method of making a semiconductor device can include providing a temporary carrier with adhesive. A first semiconductor die and a second semiconductor die can be mounted face up to the temporary carrier such that back surfaces of the first semiconductor die and the second semiconductor die are depressed within the adhesive. An embedded die panel can be formed by encapsulating at least four sides surfaces and an active surface of the first semiconductor die, the second semiconductor die, and side surfaces of the conductive interconnects in a single step. The conductive interconnects of the first semiconductor die and the second semiconductor die can be interconnected without a silicon interposer by forming a fine-pitch build-up interconnect structure over the embedded die panel to form at least one molded core unit. The at least one molded core unit can be mounted to an organic multi-layer substrate.

Abstract: A method provides a first substrate supporting an insulator layer having trenches formed therein; filling the trenches using an epitaxial growth process with at least semiconductor material; planarizing tops of the filled trenches; forming a first layer of dielectric material on a resulting planarized surface; inverting the first substrate wafer to place the first layer of dielectric material in contact with a second layer of dielectric material on a second substrate; bonding the first substrate to the second substrate through the first and second layers of dielectric material to form a common layer of dielectric material; and removing the first substrate and a first portion of the filled trenches to leave a second portion of the filled trenches disposed upon the common dielectric layer. The removed first portion of the filled trenches contains dislocation defects. The method then removes the insulator layer to leave a plurality of Fin structures.

Abstract: An Integrated Circuit (IC) chip with a lab-on-a-chip, a method of manufacturing the lab-on-a-chip and a method of using the lab-on-a-chip for fluid flow analysis in physical systems through combination with computer modeling. The lab-on-a-chip includes cavities in a channel layer and a capping layer, preferably transparent, covering the cavities. Gates control two dimensional (2D) lattice structures acting as heaters, light sources and/or sensors in the cavities, or fluid channels. The gates and two dimensional (2D) lattice structures may be at the cavity bottoms or on the capping layer. Wiring connects the gates and the 2D lattice structures externally.

Abstract: A semiconductor device package and a method for forming the same using an improved solder joint structure are disclosure. The package includes solder joints having a thinner bottom portion than a top portion. The bottom portion is surrounded by a molding compound and the top portion is not surrounded by a molding compound. The method includes depositing and forming a liquid molding compound around an intermediate solder joint using release film, and then etching the molding compound to a reduced height. The resulting solder joint has no waist at the interface of the molding compound and the solder joint. The molding compound has a greater roughness after the etch, greater than about 3 microns, than the molding compound as formed.