Abstract: An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.

Abstract: A quantum hybridization negative differential resistance device having negative differential resistance (NDR) under a low voltage condition using a nanowire based on an organic-inorganic hybrid halide perovskite, and a circuit thereof are provided. The quantum hybridization negative differential resistance device includes a channel formed of an organic-inorganic hybrid halide perovskite crystal and electrodes formed of its inorganic framework and is connected to opposite ends of the channel.

Abstract: Semiconductor packages and methods of forming the same are disclosed. The semiconductor package includes a package, a device and a screw. The package includes a plurality of dies, an encapsulant encapsulating the plurality of dies, and a redistribution structure over the plurality of dies and the encapsulant. The device is disposed over the package, wherein the dies and the encapsulant are disposed between the device and the redistribution structure. The screw penetrates through the package and the device.

Abstract: Provided are an underfill material capable of realizing low-pressure mounting and voidless mounting, and a method for manufacturing a semiconductor device using the same. The underfill material includes a main composition containing an acrylic polymer, an acrylic monomer, and a maleimide compound, and the acrylic polymer is contained in a range of 10 parts by mass or more and 60 parts by mass or less in 100 parts by mass of the main composition, and the maleimide compound is contained in a range of 20 parts by mass or more and 70 parts by mass or less in 100 parts by mass of the main composition. Low-pressure mounting and the voidless mounting can be realized.

Abstract: The present disclosure provides a composite electrode, an acoustic sensor using the composite electrode, and a manufacturing method of the composite electrode. The composite electrode includes a conductive layer, and a semiconductor high-molecular polymer layer formed on the conductive layer. The semiconductor high-molecular polymer layer has a three-dimensional mesh structure. The acoustic sensor includes a base; the above-mentioned composite electrode formed on the base; an organic layer formed on the composite electrode; and a top electrode formed on the organic layer.

Abstract: A lateral diode with high breakdown voltage capability and a method for forming the lateral diode. The lateral diode has an anode, a cathode, a substrate having a first conductivity type, an epitaxial layer having formed on the substrate, a current region formed in the epitaxial layer and on the substrate, a first well coupled to the anode, a second well coupled to the cathode, a third well with light doping concentration formed beside the first well, and a guard ring with heavy doping concentration formed in the first well and beside the third well, and between the third well and the second well is a drift region, a lateral breakdown occurs in the third well, the drift region and the second well when a reverse voltage added on the lateral diode is equal to or higher than a breakdown voltage.

Abstract: An avalanche photodiode includes: a first semiconductor layer of a first conductivity type formed on a substrate of the first conductivity type; a second semiconductor layer of a second conductivity type formed under the first semiconductor layer; a third semiconductor layer of the first conductivity type formed in a shallow portion of the first semiconductor layer on the substrate, the third semiconductor layer having a higher concentration than an impurity concentration of the first semiconductor layer; a fourth semiconductor layer of the first conductivity type formed in a region in the first semiconductor layer immediately below the third semiconductor layer; a first contact electrically connected to the first semiconductor layer; and a second contact electrically connected to the second semiconductor layer. An impurity concentration of the fourth semiconductor layer is higher than that of the first semiconductor layer and is lower than that of the third semiconductor layer.

Abstract: The present disclosure provides a foldable display screen and a method for manufacturing same. The foldable display screen includes a substrate; a plurality of inorganic layers disposed on the substrate; a patterned metal layer sandwiched between any two of the inorganic layers; a first through-hole and a second through-hole disposed in the inorganic layers, wherein the first through-hole is disposed on the patterned metal layer, the second through-hole is positioned between two adjacent patterned metal layers, and a footprint of the first through-hole is smaller than a footprint of the patterned metal layer; and a patterned organic layer disposed on the inorganic layers to fill up the first through-hole and the second through-hole.

Abstract: A non-volatile adjustable phase shifter is coupled to a transceiver in a wireless communication device. The non-volatile adjustable phase shifter includes a non-volatile radio frequency (RF) switch. In one implementation, the non-volatile RF switch is a phase-change material (PCM) RF switch. In one approach, the non-volatile adjustable phase shifter includes a selectable transmission delay arm and a selectable transmission reference arm. A phase shift caused by the non-volatile adjustable phase shifter is adjusted when the non-volatile RF switch engages with or disengages from the selectable transmission delay arm. In another approach, the non-volatile adjustable phase shifter includes a selectable impedance element. A phase shift caused by the non-volatile adjustable phase shifter is adjusted when the non-volatile RF switch engages with or disengages from the selectable impedance element. In either approach, the phase shift changes a phase of RF signals being transmitted from or received by the transceiver.

Abstract: An avalanche photodiode (APD) is provided with a mixed composite charge layer. A novel structure of InAlAs is designed with the mixed layer. A single P-type field control layer is divided into three layers of different materials with each two forming a heterojunction structure. By controlling the relative concentration distributions and thicknesses of the first, second, and third P-type field control layers along with a mesa shape formed through chemical selective etching, a part of the second P-type field control layer is exposed to the air with a part of the first one etched out at the same time through this single structure having the mesa shape. Thus, the field of a multiplication layer is further confined at center to concentrate electric-field so that fringe field is low but not collapsed. Hence, the overall speed is increased, the intensity high, and sensitivity good while response is fast and efficiency high.

Abstract: In a transistor including an oxide semiconductor layer, an oxide insulating layer is formed so as to be in contact with the oxide semiconductor layer. Then, oxygen is introduced (added) to the oxide semiconductor layer through the oxide insulating layer, and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor layer, so that the oxide semiconductor layer is highly purified.

Abstract: An image display device includes a wavelength conversion layer containing quantum dots and a light reflecting layer provided on an observer side with respect to the wavelength conversion layer. The light reflecting layer includes, in a reflection wavelength region, a peak wavelength of a light source that emits excitation light to be used for emission of the quantum dots. The light reflecting layer is a polarizing reflective layer.

Abstract: A method for managing power quality events in an electrical system includes processing electrical measurement data from or derived from energy-related signals captured by at least one intelligent electronic device (IED) to identify at least one power quality event associated with one or more loads monitored by the at least one IED. The method also includes determining at least one means for mitigating or eliminating an impact (and/or reducing a recovery time) of the at least one identified power quality event on the electrical system based, at least in part, on an evaluation of a dynamic tolerance curve associated with one or more loads in the electrical system. The method further includes applying one or more of the at least one means for mitigating or eliminating the impact (and/or reducing the recovery time) to selected portions or zones of the electrical system.

Abstract: A semiconductor storage device according to one embodiment is the semiconductor storage device that includes: a cell array region having a plurality of memory cells; and an outer edge portion arranged at an end portion to surround the cell array region. A stacked body in which a plurality of conductive layers are stacked via a first insulating layer and which has a stair portion in which end portions of the plurality of conductive layers form a stair shape is provided inside the cell array region, the stair portion facing the outer edge portion. A center of at least one step of the stair portion has a recess directed to an inner side of the cell array region.

Abstract: A method for forming an epitaxial source/drain structure in a semiconductor device includes providing a substrate having a plurality of fins extending from the substrate. In some embodiments, a liner layer is formed over the plurality of fins. The liner layer is patterned to expose a first group of fins of the plurality of fins in a first region. In some embodiments, a first epitaxial layer is formed over the exposed first group of fins and a barrier layer is formed over the first epitaxial layer. Thereafter, the patterned liner layer may be removed. In various examples, a second epitaxial layer is selectively formed over a second group of fins of the plurality of fins in a second region.

Abstract: An optoelectronic device having a textured layer is described. In an aspect, a method may be used to produce the optoelectronic device, where the method includes epitaxially growing a semiconductor layer of the optoelectronic device on a growth substrate, and exposing the semiconductor layer to an etching process to create at least one textured surface in the semiconductor layer. The textured semiconductor layer can be referred to as a textured layer. The etching process is performed without the use of a template layer, or similar layer, configured as a mask to generate the texturing. The etching process can be done by one or more of a liquid or solution-based chemical etchant, gas etching, laser etching, plasma etching, or ion etching. The method can also include lifting the semiconductor layer of the optoelectronic device from the growth substrate by, for example, the use of an epitaxial lift off (ELO) process.

Abstract: A rapid testing read out integrated circuit (ROIC) includes phase-change material (PCM) radio frequency (RF) switches residing on an application specific integrated circuit (ASIC). Each PCM RF switch includes a PCM and a heating element transverse to the PCM. The ASIC is configured to provide amorphizing and crystallizing electrical pulses to a selected PCM RF switch. The ASIC is also configured to determine if the selected PCM RF switch is in an OFF state or in an ON state. In one implementation, a testing method using the ASIC is disclosed.

Abstract: A radio frequency (RF) switching circuit includes stacked phase-change material (PCM) RF switches. Each of the PCM RF switches includes a PCM, a heating element transverse to the PCM, and first and second heating element contacts. The first heating element contact is coupled to an RF ground, and the second heating element contact may also be coupled to an RF ground. Each of the PCM RF switches can also include first and second PCM contacts. A compensation capacitor can be coupled across the first and second PCM contacts in at least one of the PCM RF switches.

Abstract: A system for controlling a power distribution network providing power using a plurality of phases comprises an electronic processor and memory storing instructions that, when executed by the electronic processor, cause the system to receive a loss of voltage fault indication associated with a fault in the power distribution network. The electronic processor identifies a first subset of the plurality of phases associated with the loss of voltage fault indication and a second subset of the plurality of phases not associated with the loss of voltage fault indication. The first and second subsets each include at least one member. The electronic processor identifies a downstream isolation device downstream of the fault. The electronic processor sends an open command to the downstream isolation device for each phase in the first subset. The electronic processor sends a close command to a tie-in isolation device downstream of the downstream isolation device.

Abstract: A method for fabricating a semiconductor device that includes forming a mask stack over a semiconductor structure. The mask stack has a first mask layer and a second mask layer, where the second mask layer is arranged between the first mask layer and the semiconductor structure. The method further includes patterning a first pattern in the mask stack. The first pattern includes a first opening having first sidewalls formed in the first mask layer, a second opening having second sidewalls formed in the second mask layer, and a third opening having third sidewalls formed in the semiconductor structure. The first, second, and third sidewalls of the respective openings of the first pattern are formed around a central axis, where the second sidewalls of the second opening are located further away from the central axis than both the first and third sidewalls of the first and third openings, respectively.