Patents Examined by Evren Seven
  • Display apparatus and method of manufacturing the same
    Patent number: 11011589
    Abstract: A display apparatus including a display substrate, a light-emitting device on the display substrate, an encapsulation substrate on the light-emitting device and bonded to the display substrate, and a diffraction-grating layer on a top surface of the encapsulation substrate, wherein the diffraction-grating layer includes a plurality of diffraction patterns spaced apart from one another by a predetermined distance, and each of the plurality of diffraction patterns has a stacked structure of a lower layer and an upper layer, wherein the lower and upper layers include different materials.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: May 18, 2021
    Inventors: Gwangmin Cha, Woongsik Kim, Jinsu Byun, Koichi Sugitani, Saehee Han
  • Array substrate and fabricating method thereof, and display device
    Patent number: 11011584
    Abstract: An array substrate includes a back plate including planar and curved portions; a light emitting layer at the back plate including first and second light emitting units that are spaced apart from each other, and a wavelength of a light emitted by the first light emitting unit being greater than a wavelength of a light emitted by the second light emitting unit; a pixel defining layer at a first side of the back plate and between the first light emitting unit and the second light emitting unit, the pixel defining layer including a first pixel defining region on the curved portion and adjacent to the first light emitting unit and close to the planar portion; and a correction layer at a side of the first pixel defining region away from the back plate for absorbing and reflecting the light emitted by the first light emitting unit.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: May 18, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lei Chen, Wei Quan
  • Electromagnetic wave attenuator and electronic device
    Patent number: 11011474
    Abstract: According to one embodiment, an electromagnetic wave attenuator includes a plurality of magnetic layers, and a plurality of nonmagnetic layers. The plurality of nonmagnetic layers is conductive. A direction from one of the plurality of magnetic layers toward an other one of the plurality of magnetic layers is aligned with a first direction. One of the plurality of nonmagnetic layers is between the one of the plurality of magnetic layers and the other one of the plurality of magnetic layers. A first thickness along the first direction of the one of the plurality of magnetic layers is not less than ½ times a second thickness along the first direction of the one of the plurality of nonmagnetic layers.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: May 18, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, SHIBAURA MECHATRONICS CORPORATION
    Inventors: Akira Kikitsu, Yoshinari Kurosaki, Kenichiro Yamada, Shigeki Matsunaka
  • Source/drain regions in fin field effect transistors (finFETs) and methods of forming same
    Patent number: 10998313
    Abstract: An embodiment method includes forming first dummy gate stack and a second dummy gate stack over a semiconductor fin. A portion of the semiconductor fin is exposed by an opening between the first dummy gate stack and the second dummy gate stack. The method further includes etching the portion of the semiconductor fin to extend the opening into the semiconductor fin. A material of the semiconductor fin encircles the opening in a top-down view of the semiconductor fin. The method further includes epitaxially growing a source/drain region in the opening on the portion of the semiconductor fin.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Packaging structure and forming method thereof
    Patent number: 10998289
    Abstract: Packaging structure and method for forming a packaging structure are provided. A bonding layer is formed on the substrate. An improvement layer is formed on the bonding layer. The improvement layer contains openings exposing surface portions of the bonding layer at bottoms of the openings. Chips are provided and include functional surfaces. The chips are mounted on the substrate by bonding the functional surfaces of the chips to the bonding layer through the openings. Top surfaces of the chips are lower than or flush with a top surface of the improvement layer.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: May 4, 2021
    Assignee: TONGFU MICROELECTRONICS CO., LTD.
    Inventor: Lei Shi
  • Hydrogen diffusion barrier for hybrid semiconductor growth
    Patent number: 10991835
    Abstract: Semiconductor devices and methods of fabricating semiconductor devices having a dilute nitride active layer and at least one semiconductor material overlying the dilute nitride active layer are disclosed. Hybrid epitaxial growth and the use of hydrogen diffusion barrier layers to minimize hydrogen diffusion into the dilute nitride active layer are used to fabricate high-efficiency multijunction solar cells and photonic devices. Hydrogen diffusion barriers can be formed through the use of layer thickness, composition, doping and/or strain.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: April 27, 2021
    Assignee: ARRAY PHOTONICS, INC.
    Inventors: Aymeric Maros, Ferran Suarez, Jacob Thorp, Michael Sheldon, Ting Liu
  • Quantum dot device and electronic device
    Patent number: 10991899
    Abstract: A quantum dot device including an anode and a cathode facing each other; a quantum dot layer between the anode and the cathode; a hole transport layer between the anode and the quantum dot layer, the hole transport layer being configured to increase a hole transporting property from the anode to the quantum dot layer; an inorganic electron transport layer between the cathode and the quantum dot layer, the inorganic electron transport layer being configured to increase an electron transporting property from the cathode to the quantum dot layer; and an inorganic electron controlling layer between the cathode and the quantum dot layer, the inorganic electron controlling layer being configured to decrease an electron transporting property from the cathode to the quantum dot layer, and an electronic device including the same.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Woo Kim, Kun Su Park, Dae Young Chung, Eun Joo Jang
  • Semiconductor device and electronic apparatus
    Patent number: 10985081
    Abstract: The present disclosure relates to a semiconductor device and an electronic apparatus which is capable of reducing variations and deterioration of transistor characteristics. A first connection pad connected with a first wiring and a first floating metal greater than the first connection pad are formed at a bonding surface of a first substrate, whereas a second connection pad connected with a second wiring and a second floating metal greater than the second connection pad are formed at a bonding surface of a second substrate. The first floating metal and the second floating metal formed at the first substrate and the second substrate are bonded to each other. The present disclosure is applicable to a CMOS solid-state imaging device used for an imaging apparatus such as a camera, for example.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: April 20, 2021
    Assignee: SONY CORPORATION
    Inventor: Yukihiro Ando
  • Manufacturing method of smoothing a semiconductor surface
    Patent number: 10985049
    Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: April 20, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gang Wang, Charles R. Lottes, Sasha Kweskin
  • Vapor deposition mask, vapor deposition mask preparation body, method for producing vapor deposition mask, and method for producing organic semiconductor element
    Patent number: 10982317
    Abstract: There are provided a vapor deposition mask capable of satisfying both high definition and lightweight in upsizing and forming a vapor deposition pattern with high definition while securing strength, a vapor deposition mask preparation body capable of simply producing the vapor deposition mask and a method for producing a vapor deposition mask, and furthermore, a method for producing an organic semiconductor element capable of producing an organic semiconductor element with high definition. A metal mask 10 in which a slit 15 is provided and a resin mask 20 in which openings 25 corresponding to a pattern to be produced by vapor deposition are provided at a position of overlapping with the slit 15 are stacked, and the metal mask 10 has a general region 10a in which the slit 15 is provided and a thick region 10b larger in thickness than the general region.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: April 20, 2021
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Katsunari Obata, Toshihiko Takeda, Hiroshi Kawasaki, Hiroyuki Nishimura, Atsushi Maki, Hiromitsu Ochiai, Yoshinori Hirobe
  • Semiconductor device and manufacturing method thereof
    Patent number: 10985180
    Abstract: A semiconductor device includes: hole source patterns; electron source patterns located between adjacent hole source patterns; a stack structure over the hole source patterns and the electron source patterns; and channel layers penetrating the stack structure, wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: April 20, 2021
    Assignee: SK hynix Inc.
    Inventors: Jong Sung Jeon, Eun Mee Kwon, Da Som Lee, Bong Hoon Lee
  • Wiring structure and method for manufacturing the same
    Patent number: 10978417
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The at least one lower dielectric layer of the lower conductive structure is substantially free of glass fiber. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: April 13, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Display device, display panel and method of fabricating the same
    Patent number: 10978526
    Abstract: The present disclosure provides a display device, a display panel, and a fabricating method, and generally relates to the field of display technology. The display panel of the present disclosure comprises a substrate, a drive layer, a separation layer, a display device layer, and a through hole. The substrate has an opening zone, a transition zone surrounding the opening zone, and a display area surrounding the transition zone. The drive layer is disposed on a side of the substrate and covering the opening zone, the transition zone, and the display area. The separation layer is disposed on a surface of the drive layer away from the substrate and is located in the transition zone. The display panel of the present disclosure can prevent water and oxygen from entering the display area to prevent erosion of the display device.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: April 13, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chengjie Qin, Dejun Bu, Song Zhang, Tao Wang
  • Method, computer program product and system for detecting manufacturing process defects
    Patent number: 10957567
    Abstract: A system, computer program product and a method for detecting manufacturing process defects, the method may include: obtaining multiple edge measurements of one or more structural elements after a completion of each one of multiple manufacturing phases; generating spatial spectrums, based on the multiple edge measurements, for each one of the multiple manufacturing phases; determining relationships between bands of the spatial spectrums; and identifying at least one of the manufacturing process defects based on the relationships between the bands of the spatial spectrums.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: March 23, 2021
    Assignee: Applied Materials Israel Ltd.
    Inventors: Moshe Amzaleg, Ofer Adan
  • Embedded component package structure and manufacturing method thereof
    Patent number: 10950551
    Abstract: An embedded component package structure including a dielectric structure and a component is provided. The component is embedded in the dielectric structure and is provided with a plurality of conductive pillars. The conductive pillars are exposed from an upper surface of the dielectric structure and have a first thickness and a second thickness, respectively, and the first thickness is not equal to the second thickness.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 16, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Ju Liao, Chien-Fan Chen, Chien-Hao Wang
  • Display panels, methods of manufacturing the same, and display terminals
    Patent number: 10944075
    Abstract: The present disclosure relates to a display panel, a manufacturing method thereof, and a display terminal. The display panel includes an interlayer insulating layer, a planarization layer, and a pixel defining layer stacked in sequence. The display panel further includes a sub-pixel, a cathode, and a thin film encapsulation structure. The pixel defining layer is provided with an opening. The sub-pixel is disposed in the opening of the pixel defining layer, and the cathode is disposed on the pixel defining layer and covers the sub-pixel. The thin film encapsulation structure is disposed on the cathode, and the thin film encapsulation structure or the cathode is provided with a first embedded portion. The first embedded portion is embedded in the pixel defining layer and the planarization layer, and is in contact with the interlayer insulating layer.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: March 9, 2021
    Inventors: Peng Xu, Yun Cheng, Lufangyue Ji, Tongkai Zhou, Wei Du, Gang Cen
  • Semiconductor devices
    Patent number: 10943812
    Abstract: A semiconductor device includes a first trench on the device region, a first device isolation layer in the first trench and defining an active pattern of the device region, a second trench on the interface region, and a second device isolation layer in the second trench. The second isolation layer includes a buried dielectric pattern, a dielectric liner pattern on the buried dielectric pattern, and a first gap-fill dielectric pattern on the dielectric liner pattern. The buried dielectric pattern includes a floor segment on a floor of the second trench, and a sidewall segment on a sidewall of the second trench. The sidewall segment has a thickness different from a thickness of the floor segment.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: March 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Semyeong Jang, Bong-Soo Kim, Heejae Chae
  • Methods of forming microelectronic devices including dummy dice
    Patent number: 10937749
    Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Neng-Tai Shih
  • Light-emitting element, display module, lighting module, light-emitting device, display device, electronic appliance, and lighting device
    Patent number: 10930873
    Abstract: An object of one embodiment of the present invention is to provide a multicolor light-emitting element that utilizes fluorescence and phosphorescence and is advantageous for practical application. The light-emitting element has a stacked-layer structure of a first light-emitting layer containing a host material and a fluorescent substance, a separation layer containing a substance having a hole-transport property and a substance having an electron-transport property, and a second light-emitting layer containing two kinds of organic compounds that form an exciplex and a substance that can convert triplet excitation energy into luminescence. Note that a light-emitting element in which light emitted from the first light-emitting layer has an emission spectrum peak on the shorter wavelength side than an emission spectrum peak of the second light-emitting layer is more effective.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: February 23, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Nobuharu Ohsawa, Yusuke Nonaka, Takahiro Ishisone, Satoshi Seo, Takuya Kawata
  • Device and methods for the transfer of chips from a source substrate onto a destination substrate
    Patent number: 10923460
    Abstract: A device for the transfer of chips from a source substrate onto a destination substrate, including: a source substrate having a lower surface and an upper surface; and a plurality of elementary chips arranged on the upper surface of the source substrate, wherein each elementary chip is suspended above the source substrate by at least one breakable mechanical fastener, said at least one breakable mechanical fastener having a lower surface fastened to the upper surface of the source substrate and an upper surface fastened to the lower surface of the chip.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: February 16, 2021
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Stéphane Caplet, Laurent Mollard