Patents Examined by Faisal M Zaman
  • Patent number: 12204913
    Abstract: A system and method for installation and configuration of computing resources where a local attribute that uniquely identifies a deployed device is used with a query to a remote domain name server to receive one or more responses to the query, the responses from the domain name server providing the steps and operations to implement an expected local configuration which is then validated and implemented in each the deployed device.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: January 21, 2025
    Inventors: Carlo Daffara, Lorenzo Faleschini
  • Patent number: 12197970
    Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: January 14, 2025
    Assignee: HyperX Logic, Inc.
    Inventors: Carl S. Dobbs, Michael R. Trocino, Keith M. Bindloss
  • Patent number: 12189450
    Abstract: An electronic control unit includes a microcomputer configured to be started by a plurality of starting factors, in which different operation modes are associated with each of the starting factors, and a resource is associated with each of the operation modes. The microcomputer identifies a starting factor in an initialization process started by the starting factor, and selects and executes an operation mode associated with the starting factor identified. When another starting factor is generated during execution of the operation mode, the microcomputer stops execution of the operation mode and restarts, and then executes an operation mode associated with the other starting factor.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: January 7, 2025
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Takuya Kobayashi, Daisuke Furuya
  • Patent number: 12182635
    Abstract: Devices and techniques for CHAINED RESOURCE LOCKING are described herein. Threads form a last-in-first-out (LIFO) queue on a resource lock to create a chained lock on the resource. A data store representing the lock for the resource holds the previous thread's identifier, enabling a subsequent thread to wake the previous thread using the identifier when the subsequent thread releases the lock. Generally, the thread releasing the lock need not interact with the data store, reducing contention for the data store among many threads.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: December 31, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Patrick Estep, Tony M. Brewer
  • Patent number: 12182580
    Abstract: A method, apparatus and storage medium for starting up peripheral component interconnect express (PCIE) device are provided. According to the method, a basic input/output system (BIOS) attempts to verify firmware of a PCIE device to determine whether the firmware of the PCIE device is tampered with. Moreover, the BIOS may only start up a PCIE device with firmware that succeeds in the verification. Therefore, a computer device is prevented from starting up a PCIE device with firmware that is tampered with, thereby reducing the security risk caused by the PCIE device to the computer device.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: December 31, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Yutao Li
  • Patent number: 12164930
    Abstract: Embodiments of the systems and methods disclosed herein relate to a modem having a processor including a Unified Extensible Firmware Interface (UEFI) driver. The UEFI driver can be configured to provide a software interface between an operating system for the modem and firmware for the modem. The modem can include a boot diagnostic driver configured to run from the UEFI driver and execute a diagnostic test when the modem is booting up. The boot diagnostic driver can be configured to generate a signal based on a result of the diagnostic test.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: December 10, 2024
    Assignee: ARRIS Enterprises LLC
    Inventors: Linzhou Cai, Yongqiang Ye, Shenxia Tan, Yongqin Zuo, Dongting Zhang
  • Patent number: 12153681
    Abstract: According to embodiments of the present disclosure, an Information Handling System (IHS), systems and methods for identifying firmware versions of a firmware image using SPDM alias certificates are disclosed. In one embodiment, an IHS includes a Security Protocol and Data Model (SPDM)-enabled device conforming to a SPDM specification, and computer-executable instructions to receive a request to attest a firmware image, generate an alias certificate using a hash of the firmware and version information associated with the firmware in response to the request, and using the alias certificate, attest the version of the firmware image using the version information.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: November 26, 2024
    Assignee: Dell Products, L.P.
    Inventors: Dharma Bhushan Ramaiah, Vineeth Radhakrishnan, Mini Thottunkal Thankappan, Shinose Abdul Rahiman, Rama Rao Bisa
  • Patent number: 12141090
    Abstract: Embodiments herein provide more efficient, more flexible, and more cost-effective ways to provide additional and/or increased functionality to an information handling system. Presented herein are embodiments of an application acceleration port interface module (which embodiments may be referred to herein for convenience as “AAPIM”) into which pluggable I/O (input/output) modules may be inserted and the other ends inserted into ports of an information handling system to provide the information handling system with increase capabilities (e.g., increased resource, such as added processing, and increased services, such as new applications or accelerated services). AAPIM embodiments are versatile solutions to address application acceleration needs that can be quickly reprogrammed to address specific needs of a user.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: November 12, 2024
    Assignee: DELL PRODUCTS L.P.
    Inventors: Padmanabhan Narayanan, Raja Sathianarayan Jayakumar, Anoop Ghanwani, Per Henrik Fremrot
  • Patent number: 12142961
    Abstract: Optimized bus powered peripheral battery charging includes a circuit to initiate a change in an advanced configuration and power interface (ACPI) state in a controller allowing charging of a peripheral device battery, the circuit including a signal converter coupled between an input port and the controller to sense when a the peripheral device battery is coupled to an input port and to restrict the controller from changing ACPI state multiple times for a given peripheral device battery coupling; and a ground loop detector coupled in parallel to the signal converter between the input port and the controller to allow the controller to know that the peripheral device battery has maintained being coupled to the input port.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: November 12, 2024
    Assignee: Dell Products L.P.
    Inventors: Greg R. Fiebrich, Douglas Messick, Kyle Cross
  • Patent number: 12135581
    Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: November 5, 2024
    Assignee: Intel Corporation
    Inventors: David J. Harriman, Debendra Das Sharma, Daniel S. Froelich, Sean O. Stalley
  • Patent number: 12135974
    Abstract: Some embodiments of the invention provide a method for generating custom system templates to define new system types. For a particular system type, the method defines at least a manifest file that specifies a set of properties of the particular system type. The method compresses the defined manifest file to create a custom system template package for the particular system type. The method uploads the custom system template package to an authorization service in order to instantiate a new system of the particular system type.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: November 5, 2024
    Assignee: STYRA, INC.
    Inventors: Stan Lagun, Timothy L. Hinrichs, Teemu Koponen
  • Patent number: 12135676
    Abstract: A serial bus repeater includes a port circuit and a low power state detection circuit. The port circuit is configured to communicate via a serial bus. The low power state detection circuit includes a power state transaction identification circuit and a bus state identification circuit. The power state transaction identification circuit is configured to identify a power state transaction on the serial bus. The power state transaction is indicative of entering a reduced power state. The bus state identification circuit is configured to identify a value of termination resistance on the serial bus that is indicative of entering the reduced power state.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: November 5, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Win Naing Maung, Suzanne Mary Vining
  • Patent number: 12130715
    Abstract: A discrete VRM card includes a first VRM controller and a second VRM controller. The discrete VRM card also includes a first primary power stage, a second primary power stage, and an adaptable spare stage. The discrete VRM card includes a first switch and a second switch. Closing the first switch connects the adaptable spare converter with an output of the first primary power stage. Closing the second switch connects the adaptable spare converter an output of the second primary power stage.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: October 29, 2024
    Assignee: International Business Machines Corporation
    Inventors: Justin Henspeter, Michael Lee Miller, Eric B. Swenson, Jordan Keuseman
  • Patent number: 12126457
    Abstract: An Active Power Edge device may include a power strip comprising electrical outlets; a MQ Telemetry Transport (MQTT) client to communicate with a broker and to receive a configuration from the broker; and a monitor to enable the electrical outlets per the configuration, to perform status checks and to report a result of the status checks to the broker via the MQTT client, wherein the configuration includes an outlet device and a status check definition, and the status checks are performed per the status check definition.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: October 22, 2024
    Assignee: Hughes Network Systems, LLC
    Inventors: Carl Malone, Ronald Paul Alder, Quinn Jensen, T. Kelly Bradford, Mike Balzotti, Rahul Rode, Ben Dorton, Kim Clark, John Hundley
  • Patent number: 12117960
    Abstract: Systems, methods, and apparatuses associated with an approximate majority based data bus inversion technique are disclosed. A method comprises obtaining, at a first device connected by a plurality of lanes to a second device, original data comprising first bits and second bits, where the first bits are to be transmitted in a new clock cycle via first lanes of the plurality of lanes, and the second bits are to be transmitted in the new clock cycle via second lanes of the plurality of lanes. The method further includes determining whether a first criterion associated with the first bits is met, determining whether a second criterion associated with the second bits is met, and transmitting an inverted version of the original data via the plurality of lanes based, at least in part, on determining that the first criterion and the second criterion are met.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Narasimha Lanka, Lakshmipriya Seshan, Gerald S. Pasdast, Zuoguo Wu
  • Patent number: 12105571
    Abstract: Systems and methods for managing consumption of alternating-current (AC) power by an Information Handling System (IHS). In a non-limiting embodiment, an IHS may include: a heterogeneous computing platform comprising a plurality of devices and a memory, the memory having a plurality of sets of firmware instructions, where each of the sets, upon execution by a respective device, enables that device to provide a corresponding firmware service, and where at least one of the devices operates as an orchestrator configured to: execute or instruct one or more devices to execute one or more Artificial Intelligence models usable to characterize usage profiles based, at least in part, upon context or telemetry data received from at least a subset of the plurality of devices; and, based upon the usage profiles, determine whether to allow a battery to power the IHS at least partially while the IHS is coupled to an AC power source.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: October 1, 2024
    Assignee: Dell Products, L.P.
    Inventors: Srikanth Kondapi, Daniel L. Hamlin, Nikhil Manohar Vichare
  • Patent number: 12105552
    Abstract: It is provided a synchronization system capable of managing execution of synchronization for clocks to be mounted on various devices. A synchronization system of clocks comprising: a leader device; a follower device capable of establishing communication connection with the leader device; and a server apparatus capable of establishing communication connection with the leader device and/or the follower device, the system further comprising: a time deviation calculator configured to calculate a time deviation between the leader device and the follower device; and a time corrector configured to correct a time in the follower device based on the calculated time deviation, wherein the synchronization system executes the time deviation calculator and/or the time corrector when the server apparatus generates, transmits, and/or receives predetermined information.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: October 1, 2024
    Assignee: NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY
    Inventors: Nobuyasu Shiga, Satoshi Yasuda
  • Patent number: 12105570
    Abstract: Systems and methods for battery management in heterogenous computing platforms. In a non-limiting embodiment, an Information Handling System may include a heterogeneous computing platform having a plurality of devices and a memory coupled to the platform, where the memory includes a plurality of sets of firmware instructions, each of the sets of firmware instructions, upon execution by a respective device among the plurality of devices, enables the respective device to provide a corresponding firmware service, and at least one of the plurality of devices operates as an orchestrator configured to: receive context or telemetry data from at least a subset of the plurality of devices; and execute or instruct one or more selected devices among the plurality of devices to execute one or more Artificial Intelligence models usable to manage a charging or discharging operation of a battery based, at least in part, upon the context or telemetry data.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: October 1, 2024
    Assignee: Dell Products, L.P.
    Inventors: Nikhil Manohar Vichare, Srikanth Kondapi, Daniel L. Hamlin
  • Patent number: 12099395
    Abstract: An electronic device is provided. The electronic device includes a connector including multiple conductive terminals, a battery, and a power control circuit electrically connected to the connector and the battery, wherein the power control circuit controls a value corresponding to electrical information on a first conductive terminal among the multiple conductive terminals so that a first time interval during which a first value is maintained and a second time interval during which a second value is maintained after the first time interval are alternated for each time interval among the multiple time intervals, identify, in response to the connection of the electronic device to the external device through the cable connected to the connector, whether a size of a time, during which the value is maintained as one of the first value or the second value, is smaller than a designated value, and select a first method.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: September 24, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyoungwon Kim
  • Patent number: 12099849
    Abstract: An example computing device includes a non-volatile memory to store Basic Input/Output Systems (BIOS) data of the computing device, an audio codec, and a controller. The controller is to: receive a command from a provisioning device at the audio codec; and transfer a copy of the BIOS data between the controller and the memory based on the command.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: September 24, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Wei Ze Liu, Lan Wang, Chengkai Yeh, Christian Pena