Abstract: Embodiments for communicating between first and second hosts according to CXL.mem and CXL.cache protocols. A computer translates a CXL.mem M2S RwD with a Tag, received by a CXL Type 2 or Type 3 device (EP1) from the first host, to a CXL.cache D2H Req with a CQID. A CXL Type 1 or Type 2 device (EP2) sends the D2H Req to the second host, and receives a CXL.cache H2D Rsp with the CQID and a UQID. EP1 sends a CXL.mem S2M NDR with the Tag to the first host, and EP2 sends a CXL.cache D2H Data message with the UQID to the second host. Optionally, EP1 receives and terminates CXL.io/PCIe Configuration Request TLPs from the first host, the M2S RwD further includes a first physical address and Data, and the D2H Req further includes a second physical address.

Abstract: A wireless device includes a voltage regulator circuit configured to generate a voltage signal of a first input voltage, and a wireless baseband processing circuitry (WBPC) coupled to the voltage regulator circuit to receive the voltage signal. The WBPC is configured to process signals for transmission or reception using wireless technology. The WBPC includes a sub-system processor circuit configured to detect a wireless bandwidth of an application executing on an application processor of the wireless device; determine a second input voltage based on the wireless bandwidth of the application and a maximum voltage supported by the WBPC; and encode a feedback signal for communication to the voltage regulator circuit. The feedback signal causes adjustment of the voltage signal to the second input voltage.

Abstract: A cost estimation tool in a system for implementing an operation unit graph on a reconfigurable processor is presented as well as a method of operating a cost estimation tool for determining scaled logical edge bandwidths in an operation unit graph in preparation of placing and routing the operation unit graph onto a reconfigurable processor. The cost estimation tool may be configured to receive the operation unit graph, divide the operation unit graph in first and second subgraphs, determine maximum latencies of the first and second subgraphs, and determine a scaled logical edge bandwidth of a logical edge that couples a first logical unit of M logical units in the first subgraph with a second logical unit of N logical units in the first subgraph based on M, N, and scaled bandwidth limits of the M and N logical units.

Abstract: A sorting tool for determining an ordered sequence of nodes in an operation unit graph for placing and routing the operation unit graph onto a reconfigurable processor is presented as well as a method of operating a sorting tool for determining an ordered sequence of nodes in an operation unit graph for placing and routing the operation unit graph onto a reconfigurable processor. The sorting tool is configured to receive the operation unit graph including a set of unsorted nodes and edges that interconnect nodes in the set of unsorted nodes, determine an ordered sequence of the nodes in the operation unit graph, and provide the ordered sequence of nodes for the placing and routing of the operation unit graph onto the reconfigurable processor.

Abstract: A Peripheral Component Interconnect Express (PCIe) system is configured to determine when the frequency of link speed switching needed to service incoming and upcoming client requests is too high. The system is also configured to determine a modest link speed to be used to service incoming and upcoming client requests in cases where the link speed switching that will be needed is too high and causes the incoming and upcoming client requests to be serviced at the modest link speed instead of at the link speeds associated with the predefined BWs of the clients. By doing this when the frequency of link speed switching needed is too high, the PCIe system achieves better throughput while also reducing power consumption.

Abstract: A technique for operating an auxiliary processing device is provided. The technique includes based on a first request specifying a handle received from a client, requesting work be performed via a first auxiliary processing device mapped to the handle; responsive to restoration from hibernation, updating a mapping for the handle to refer to a second auxiliary processing device; and based on a second request specifying the handle received from the client, requesting work be performed via the second auxiliary processing device.

Abstract: According to an embodiment, a semiconductor memory device includes a first pin, a first receiving circuit, and a first terminating circuit. The first pin receives a first signal and a second signal having a smaller amplitude than the first signal. The first receiving circuit is connected to the first pin and outputs, based on a comparison between the first signal and a first voltage, a third signal. The first receiving circuit also outputs, based on a comparison between the second signal and a second voltage, a fourth signal having a smaller amplitude than the third signal. The first terminating circuit is connected to the first pin. The first terminating circuit is disabled if the first pin receives the first signal, and enabled if the first pin receives the second signal.

Abstract: Systems and methods for optimizing a pipeline are described. A system can generate at least one pair of single flux quantum (SFQ) clock signals based on a stream of SFQ pulses. Each pair of SFQ clock signals can include a first SFQ clock signal and a second SFQ clock signal that is out of phase with the first SFQ clock signal. The second SFQ clock signal can have the same frequency as the first SFQ clock signal. The system can define, for each pair of SFQ clock signals, a first clock cycle and a second clock cycle based on the first SFQ clock signal and the second SFQ clock signal. The second clock cycle can be greater than the first clock cycle. The system can assign the first and second clock cycles to different stages of a pipeline based on delays by the different stages.

Abstract: The present disclosure discloses a data processing method and system, an apparatus, and a computer-readable storage medium, which relate to the field of storage. The data processing method includes determining a root port of a peripheral component interconnect express (PCIe) switch X (PSX) based on a connection topology of a PCIe; controlling a central processing unit (CPU) corresponding to the root port to monitor a read state of memory-mapped remote procedure calls (MRPC) data using a completion timeout mechanism; and in response to the read state being a timeout state, discarding read MRPC data.

Abstract: An information handling system detects a transition of a signal from a magnetic sensor, wherein the transition of the signal indicates a change of a lid of the information handling system from a first state to a second state. The system may determine an angle of the lid based on information from an inertial sensor, and confirm whether the lid is at the second state based on the determined angle of the lid. In response to a confirmation that the lid is at the second state, the system may perform a power sequence.

Abstract: Example memory controllers are disclosed. An example memory controller may include a PHY module including a first PHY terminal connected to a plurality of pins of a device connector, a MAC module including a first MAC terminal that is enabled to form a first lane with the first PHY terminal, and a second MAC terminal that is disabled without being connected to the first PHY terminal, a switch controller configured to receive a signal of a host connector connected to the device connector from at least one of the plurality of pins and output a switch signal in response to the signal of the host connector, and a switch configured to disable the second MAC terminal and form the first lane by connecting the first PHY terminal to the first MAC terminal in response to the switch signal.

Abstract: Each of the nodes stores a number, referred to herein as a generation number, which is updated whenever the respective node undergoes a reset and restart from checkpoint. Since the nodes of the system participate in the same reset event, at most times, each generation number held by a node will be the same across the system. However, in some cases, when one node resets before another node, the generation numbers between those two nodes will differ. The data frames sent between the nodes each comprise a generation number of the sending node, which is checked by the recipient and only accepted if the generation number in the frames matches the generation number of the recipient node.

Abstract: Various embodiments include methods performed by a processor for managing voltage droop margins of a power distribution network (PDN). Various embodiments may include receiving, by a processor from a first client powered by a shared power rail within the PDN, a first requested performance corner, receiving, by the processor from a second client powered by the shared power rail, a second requested performance corner, determining by the processor a first peak current value based on the first requested performance corner, determining by the processor a second peak current value based on the second requested performance corner, determining by the processor a system voltage droop margin based on the first peak current value, the second peak current value, and an impedance value of the PDN, and adjusting a voltage of the shared power rail based on the system voltage droop margin.

Abstract: A first command is scheduled on a command bus, where the first command requires use of a data bus resource at a first time period after scheduling the first command. Prior to the first time period, a second command is identified according to a scheduling policy. A determination is made whether scheduling the second command on the command bus will cause a conflict in usage of the at least one data bus resource. In response to determining that scheduling the second command will cause the conflict in usage, a third lower-priority command is identified for which scheduling on the command bus will not cause the conflict in usage. The third command is scheduled on the command bus prior to scheduling the second command, even though it has lower priority than the second command.

Abstract: A power negotiation method for power over Ethernet, power sourcing equipment, a system, and a storage medium are provided, and belong to the field of power over Ethernet technologies. The power sourcing equipment includes a plurality of power supply ports and a plurality of data ports. The power sourcing equipment supplies power to a connected powered device through the power supply port, and transmits data to the connected powered device through the data port. In this way, the power supply port can meet a data transmission requirement when a data transmission rate increases. According to the application, when a first power supply port and a first data port are connected to a first powered device, the power sourcing equipment can perform power negotiation with first power sourcing equipment through the first data port based on port feature information of the first power supply port.

Abstract: The present disclosure provides an information reading method, a device, a cable, a charging system, and a computer storage medium. The device includes a device control chip and a first interface. The first interface includes a first-type data signal terminal and a second-type data signal terminal. The first-type data signal terminal is connected to a power supply terminal of a communication control chip of the cable. The second-type data signal terminal is connected to a data signal terminal of the communication control chip. The device control chip is configured to control the first-type data signal terminal to be in a first output state. The first-type data signal terminal is configured to provide, when in the first output state, a first voltage to the power supply terminal, to supply power to the communication control chip.

Abstract: A clock generating circuit includes an input terminal, configured to receive a clock signal; an output terminal, configured to output an output signal; a gray counter circuit, coupled to the input terminal, and configured to divide the clock signal to produce a first output signal; and a shielding circuit, coupled to the input terminal, the gray counter circuit and the output terminal, and configured to shield a glitch in the first output signal to generate the output signal according to the clock signal.

Abstract: The system on a chip includes at least a first digital domain configured to be reinitialized by a first reinitialization signal, a second digital domain and an interface circuit. The interface circuit includes a starting register in the first digital domain, a destination register in the second digital domain and a synchronization circuit in the first digital domain. The interface circuit is configured to transfer data from the starting register to the destination register upon command of a control signal transmitted by the synchronization circuit. The starting register and the synchronization circuit are configured to not be reinitialized by the first reinitialization signal.

Abstract: A method including identifying the operation mode of the electronic device as a first operation mode, sensing a change of setting corresponding to the first operation mode, determining whether to update setting information about the setting, based on at least one of a changing pattern or a change history of a user, and when the operation mode is identified later as the first operation mode, providing the user with the first operation mode with the plurality of updated settings including the setting information about the updated setting is provided.

Abstract: A computing device includes a host processor to execute a host driver to create a host-side interface, the host-side interface emulating a first Ethernet interface, assign the host-side interface a first medium access control (MAC) address and a first Internet Protocol (IP) address. Memory components are disposed on a substrate. A memory channel network (MCN) processor is disposed on the substrate and coupled between the memory components and the host processor. The MCN processor is to execute an MCN driver to create a MCN-side interface, the MCN-side interface emulating a second Ethernet interface. The MCN processor is to assign the MCN-side interface a second MAC address and a second IP address, which identify the MCN processor as a MCN network node to the host processor.