Abstract: Embodiments herein provide more efficient, more flexible, and more cost-effective ways to provide additional and/or increased functionality to an information handling system. Presented herein are embodiments of an application acceleration port interface module (which embodiments may be referred to herein for convenience as “AAPIM”) into which pluggable I/O (input/output) modules may be inserted and the other ends inserted into ports of an information handling system to provide the information handling system with increase capabilities (e.g., increased resource, such as added processing, and increased services, such as new applications or accelerated services). AAPIM embodiments are versatile solutions to address application acceleration needs that can be quickly reprogrammed to address specific needs of a user.

Abstract: Optimized bus powered peripheral battery charging includes a circuit to initiate a change in an advanced configuration and power interface (ACPI) state in a controller allowing charging of a peripheral device battery, the circuit including a signal converter coupled between an input port and the controller to sense when a the peripheral device battery is coupled to an input port and to restrict the controller from changing ACPI state multiple times for a given peripheral device battery coupling; and a ground loop detector coupled in parallel to the signal converter between the input port and the controller to allow the controller to know that the peripheral device battery has maintained being coupled to the input port.

Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.

Abstract: A serial bus repeater includes a port circuit and a low power state detection circuit. The port circuit is configured to communicate via a serial bus. The low power state detection circuit includes a power state transaction identification circuit and a bus state identification circuit. The power state transaction identification circuit is configured to identify a power state transaction on the serial bus. The power state transaction is indicative of entering a reduced power state. The bus state identification circuit is configured to identify a value of termination resistance on the serial bus that is indicative of entering the reduced power state.

Abstract: Some embodiments of the invention provide a method for generating custom system templates to define new system types. For a particular system type, the method defines at least a manifest file that specifies a set of properties of the particular system type. The method compresses the defined manifest file to create a custom system template package for the particular system type. The method uploads the custom system template package to an authorization service in order to instantiate a new system of the particular system type.

Abstract: A discrete VRM card includes a first VRM controller and a second VRM controller. The discrete VRM card also includes a first primary power stage, a second primary power stage, and an adaptable spare stage. The discrete VRM card includes a first switch and a second switch. Closing the first switch connects the adaptable spare converter with an output of the first primary power stage. Closing the second switch connects the adaptable spare converter an output of the second primary power stage.

Abstract: An Active Power Edge device may include a power strip comprising electrical outlets; a MQ Telemetry Transport (MQTT) client to communicate with a broker and to receive a configuration from the broker; and a monitor to enable the electrical outlets per the configuration, to perform status checks and to report a result of the status checks to the broker via the MQTT client, wherein the configuration includes an outlet device and a status check definition, and the status checks are performed per the status check definition.

Abstract: Systems, methods, and apparatuses associated with an approximate majority based data bus inversion technique are disclosed. A method comprises obtaining, at a first device connected by a plurality of lanes to a second device, original data comprising first bits and second bits, where the first bits are to be transmitted in a new clock cycle via first lanes of the plurality of lanes, and the second bits are to be transmitted in the new clock cycle via second lanes of the plurality of lanes. The method further includes determining whether a first criterion associated with the first bits is met, determining whether a second criterion associated with the second bits is met, and transmitting an inverted version of the original data via the plurality of lanes based, at least in part, on determining that the first criterion and the second criterion are met.

Abstract: It is provided a synchronization system capable of managing execution of synchronization for clocks to be mounted on various devices. A synchronization system of clocks comprising: a leader device; a follower device capable of establishing communication connection with the leader device; and a server apparatus capable of establishing communication connection with the leader device and/or the follower device, the system further comprising: a time deviation calculator configured to calculate a time deviation between the leader device and the follower device; and a time corrector configured to correct a time in the follower device based on the calculated time deviation, wherein the synchronization system executes the time deviation calculator and/or the time corrector when the server apparatus generates, transmits, and/or receives predetermined information.

Abstract: Systems and methods for battery management in heterogenous computing platforms. In a non-limiting embodiment, an Information Handling System may include a heterogeneous computing platform having a plurality of devices and a memory coupled to the platform, where the memory includes a plurality of sets of firmware instructions, each of the sets of firmware instructions, upon execution by a respective device among the plurality of devices, enables the respective device to provide a corresponding firmware service, and at least one of the plurality of devices operates as an orchestrator configured to: receive context or telemetry data from at least a subset of the plurality of devices; and execute or instruct one or more selected devices among the plurality of devices to execute one or more Artificial Intelligence models usable to manage a charging or discharging operation of a battery based, at least in part, upon the context or telemetry data.

Abstract: Systems and methods for managing consumption of alternating-current (AC) power by an Information Handling System (IHS). In a non-limiting embodiment, an IHS may include: a heterogeneous computing platform comprising a plurality of devices and a memory, the memory having a plurality of sets of firmware instructions, where each of the sets, upon execution by a respective device, enables that device to provide a corresponding firmware service, and where at least one of the devices operates as an orchestrator configured to: execute or instruct one or more devices to execute one or more Artificial Intelligence models usable to characterize usage profiles based, at least in part, upon context or telemetry data received from at least a subset of the plurality of devices; and, based upon the usage profiles, determine whether to allow a battery to power the IHS at least partially while the IHS is coupled to an AC power source.

Abstract: An electronic device is provided. The electronic device includes a connector including multiple conductive terminals, a battery, and a power control circuit electrically connected to the connector and the battery, wherein the power control circuit controls a value corresponding to electrical information on a first conductive terminal among the multiple conductive terminals so that a first time interval during which a first value is maintained and a second time interval during which a second value is maintained after the first time interval are alternated for each time interval among the multiple time intervals, identify, in response to the connection of the electronic device to the external device through the cable connected to the connector, whether a size of a time, during which the value is maintained as one of the first value or the second value, is smaller than a designated value, and select a first method.

Abstract: An example computing device includes a non-volatile memory to store Basic Input/Output Systems (BIOS) data of the computing device, an audio codec, and a controller. The controller is to: receive a command from a provisioning device at the audio codec; and transfer a copy of the BIOS data between the controller and the memory based on the command.

Abstract: The present disclosure relates to a method of communication via serial bus, comprising: the conveyance by the serial bus of a frame comprising at least two consecutive cycles of a dominant state followed by a recessive state, the recessive states and dominant states having durations comprised between 2 and 5 times the duration of a data bit conveyed by the serial bus, and preferably above 1.8 ?s; and the detection by one or more circuits coupled to the serial bus of at least a part of the frame for triggering the passage from a sleep state to a wake state of the one or more circuits.

Abstract: The present invention relates to fast start-up of powered devices (22) connected to a power sourcing equipment (10?) in a Power over Ethernet system (100). A stored voltage-current profile of an initial powering phase of a powered device (22) is provided. A voltage level provided to the powered device (22) in a subsequent initial powering phase of the powered device (22) is adjusted as long as a value corresponding to a current voltage level of a voltage-current profile of the subsequent initial powering phase deviates less than a predetermined threshold level from its corresponding value of the stored voltage-current profile of the initial powering phase of the powered device (22) and until a predetermined voltage level is reached. This can allow detecting whether a previously connected powered device (22) was replaced by another powered device (22) and to immediately start-up an unchanged powered device (22) with previously used operation parameters.

Abstract: According to various aspects, a controller may be configured to: control a transmission over a single-wire interface of an instruction corresponding to a high-current operation; and control an electrical behavior of a charging path to provide current at the single-wire interface during a time period corresponding to an execution of the instructed high-current operation.

Abstract: The computer system responds to a first trigger event to enter a partial off state in which a boot cycle is required to return to a working state. A device plugged into a serial bus port can be charged in the partial off state. A configuration register or runtime environment controls whether the computer system enters the partial off state in response to a trigger event. The computer system stays in the partial off state until another trigger event returns the computer system to the working state. In some implementations, the computer system leaves the partial off state and enters the shutdown state after an unplug event, a predetermined amount of time after an unplug event, a predetermined amount of time after entering the partial off state, a predetermined amount of time after charging of a device is complete, or any combination of such events.

Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.

Abstract: A battery management system includes: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device and a second slave BMIC device that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device is coupled to the master BMIC through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device and the second slave BMIC device are configured to be coupled to a first battery pack and a second battery pack, respectively.

Abstract: This application is directed to frequency controlling in an electronic device that includes a selector, a clock generated, and a controller. The selector selects one of a first reference signal and a second reference signal as an input signal having an input phase. The clock generator receives the input signal and generates a periodic signal, and the periodic signal has an output phase that matches the input phase of the input signal. While the first reference signal is selected as the input signal, the controller identifies a temporal range including a peak instant at which the second reference signal reaches a peak frequency, select a switching instant within the temporal range based on a known temporal position of the peak instant with respect to the temporal range, and control the selector to select the second reference signal as the input signal at the switching instant.