Abstract: An electronic device (201) of a transportation means comprises a power bus input interface (202), a power bus output interface (203), and a data bus interface (204). The device comprises voltage reducing means (205) for selectively performing a controlled voltage reduction between the power bus input interface (202) and the power bus output interface (203). The reduced operating voltage is lower than the operating voltage received via the power bus input interface (202) but higher than zero. The device is arranged to use (1201, 1202) said voltage reducing means depending in a predetermined manner on whether or not the device has performed addressing operations to carry out addressed data communication by means of said data bus.

Abstract: An example device includes a data port to provide a data channel to a host and a processor coupled to the data port. The processor includes an operational mode and a low-power mode in which the processor is to perform fewer operations than in the operational mode. The processor is to execute instructions in the operational mode and to update the instructions with updated instructions received via the data channel in the operational mode. The device further includes a side channel to receive a signal from the host to trigger the processor to switch from the low-power mode to the operational mode and to initiate update of the instructions with the updated instructions.

Abstract: An information processing apparatus includes a memory, a control unit to accept an access to the memory, a power supply circuit to supply a voltage to the memory and the control unit, a detection circuit to detect a drop in the voltage, a discharge circuit, and a delay circuit. The discharge circuit discharges a charge on a voltage supply line extending between the power supply circuit and the memory. The delay circuit delays receipt of a control signal by the discharge circuit for a predetermined period after the discharge circuit receives a charge discharge instruction from the control unit. The control signal is to control discharging the supply line charge. The discharge circuit discharges supply line charges per a control signal based on detection of a drop in the voltage by the detection circuit and based on the delay of the control signal delayed by the delay circuit.

Abstract: An electronic device includes an interface with a first terminal, a second terminal, and a power supply. A voltage divider includes series-connected resistors, between the first terminal and ground voltage. A first programmable fuse is provided and the voltage divider converts the first signal to a different voltage level according to the state of the first programmable fuse. A first transistor has a gate receiving the converted first signal and a second transistor has a gate electrically connected to the second terminal and a source-drain terminal of the first transistor. The second transistor is off when the first transistor is on. A fuse-type switching element is connected between the power supply terminal a power supply circuit. A control terminal of the fuse-type switching element is connected to a source-drain terminal of the second transistor switches conduction state according to whether the second transistor is on or off.

Abstract: An electronic device is disclosed. In addition, various embodiments identified through the specification are available. An electronic device disclosed in the disclosure includes a connector that is connected to a docking device, a first interface module supporting a display port protocol, a second interface module supporting a UFS protocol, a third interface module supporting a USB protocol, a switch located between the connector and the first interface module and the second interface module, a processor that controls the switch, and a memory electrically connected to the processor, wherein the memory stores instructions that, when executed by the processor, cause the processor to control the switch such that the first interface module is connected to the connector, receive a first signal requesting a change of an interface module from the docking device through the third interface module, and control the switch such that the second interface module is connected to the connector.

Abstract: An information processing apparatus includes: a processing unit configured to write setting data to be used for boot processing by BIOS (Basic Input Output System) in a predetermined area of a non-volatile memory in an order of changing, and execute the boot processing based on the setting data; a writing unit configured to write at least one tag in the predetermined area of the non-volatile memory at a predetermined timing during the boot processing, the tag corresponding to the timing; and an instruction unit configured to instruct the processing unit to execute the boot processing using setting data written before the tag in the predetermined area of the non-volatile memory.

Abstract: Disclosed are an HMC controller and a controlling method on a CPU side and an HMC side for a low power mode, and a recording medium related thereto. The CPU side HMC controller includes a plurality of link units, each of which includes a link master for storing request packets of a CPU in a request buffer and transmitting the request packets to an HMC side HMC controller in the order that they are stored; and a link slave for storing the request packets received from the HMC side HMC controller in a response buffer and transmitting the request packets to the CPU in the order that they are stored.

Abstract: There is provided a method and system (200) for power management of an event-based processing system (100). The system (200) is configured to obtain information representing a history of arrival times of events, wherein the information comprises arrival timestamps of the events. The system (200) is configured to determine a measure for power management based on the timestamps of at least two events represented in the information. The system (200) is also configured to perform power management based on the determined measure.

Abstract: A system for controlling power settings is provided that includes a plurality of components, each component configured to implement a power control algorithm. A controller is coupled to each component and configured to control a power state of each component as a function of the power control algorithm for each component. The controller comprises a state machine having a plurality of states, wherein the power control algorithm of each component is controlled by the controller as a function of a state of the state machine.

Abstract: An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.

Abstract: A multi-port power delivery system includes a first universal serial bus (USB) port, a second USB port, a first power conversion unit, a second power conversion unit, a power delivery control circuit and a switch circuit. The first USB port is configured to output power delivered to a first power path. The second USB port is configured to output power delivered to a second power path. The first power conversion unit has a first output terminal coupled to the first power path. The second power conversion unit has a second output terminal coupled to the second power path. The power delivery control circuit generates a switch control signal according to first connection information on the first USB port and second connection information on the second USB port. The switch circuit selectively couples the first output terminal to the second output terminal according to the switch control signal.

Abstract: A bus system is provided. The bus system includes a master device and a plurality of slave devices electrically connected to the master device. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. When the alert handshake control line is at a first voltage level and a first slave device want to communicate with the master device, the first slave device controls the alert handshake control line to a second voltage level via the alert handshake pin, such that the slave devices enter a synchronization stage. Among phases of each assignment period, in a first phase corresponding to the first slave device, the first slave device controls the alert handshake control line to the second voltage level via the alert handshake pin.

Abstract: A network port connector ejection system includes a computing device connector that is connected to a network port connector. A retention device in the network port connector ejection system is configured to engage the network port connector to secure the network port connector to the computing device connector. A retention device release subsystem in the network port connector ejection system is coupled to the retention device and is configured to be actuated to release the retention device from engagement with the network port connector. A network port connector ejection subsystem in the network port connector ejection system is configured to engage the network port connector, while the retention device release subsystem is actuated to release the retention device from engagement with the network port connector, to disconnect the network port connector from the computing device connector.

Abstract: An information processing system includes multiple processing units the number of which is at least three and multiple communication paths that allow the multiple processing units to mutually communicate information. When at least one of the multiple processing units is brought into a power-off state, multiple processing units that are included in the multiple processing units and that are other than the processing unit brought into the power-off state perform processing for changing one of the communication paths used by the multiple processing units other than the processing unit brought into the power-off state to a different one of the communication paths that has low power consumption.

Abstract: In embodiments, an apparatus for serial communication includes a transceiver, to receive a precoding request from a downlink receiver across a serial communication link, and to transmit data bits to the downlink receiver over the serial communication link. In embodiments, the apparatus further includes a precoder, coupled to the transceiver, to: receive scrambled data bits of a subset of the data bits to be transmitted, from a coupled scrambler, and, in response to the request from the downlink receiver, precode the scrambled data bits, and output the precoded scrambled data bits to the transceiver, for transmission to the downlink receiver across the serial communication link together with other unscrambled data bits.

Abstract: A dual-connector storage system and method for simultaneously providing power and memory access to a computing device are provided. In one embodiment, the storage system comprises a memory, a first connector, a second connector, and a controller. The controller is configured to provide power received from the second connector to a computing device connected with the first connector while also allowing the computing device to access the memory via the first connector. Other embodiments are provided.

Abstract: A method of transferring power and data between a first circuit and a second circuit is described, whereby the second circuit comprises a processing unit having an I/O terminal and an electric energy storage element, the electric energy storage element being configured to be charged by the first circuit via the I/O terminal and configured to power the processing unit, the method comprising: establishing a wired communication link between an I/O terminal of the first circuit and the I/O terminal of the second circuit; operating the I/O terminal of the second circuit as an output terminal and the I/O terminal of the first circuit as an input terminal; transmitting data via the I/O terminal of the second circuit to the I/O terminal of the first circuit by modulating an output level of the I/O terminal of the second circuit between a high level and a low level; determining whether the output level of the I/O terminal of the second circuit corresponds to the high level or the low level and, when the output leve

Abstract: A communication apparatus having power saving mode includes memory circuit unit and DMA module. The memory circuit unit is used for storing instruction and data information to be executed by microcontroller (or control circuit) of communication apparatus, and the DMA module is used to backup the instruction and data information and store such information into a memory of an electronic device when the communication apparatus receives a broadcast synchronization signal periodically sent from another communication device. During the power saving mode, the memory circuit unit is powered down. When leaving the power saving mode, the memory circuit unit is powered on, and the DMA module retrieves the instruction and data information from the memory of the electronic device and write such information into the memory circuit unit.

Abstract: The present application discloses a system level integrated circuit chip, comprising a fixed logic module and a Programmable Logic Module; the fixed logic module comprising a CPU module, a non-volatile memory module, a high speed data transmission module, an analogue-to-digital and/or digital-to-analogue conversion module; the Programmable Logic Module comprising a user-defined field programmable gate array and a programmable control module; the CPU module is interconnected with the user-defined field programmable gate array and the programmable control module; the non-volatile memory is interconnected with the user-defined field programmable gate array and the programmable control module; the analogue-to-digital and/or digital-to-analogue conversion module are connected with the user-defined field programmable gate array; and the high speed data transmission module is interconnected with the user-defined field programmable gate array.

Abstract: A Multi-Chip-Module (MCM) includes an MCM substrate and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus having a fixed data rate. The DPIC is configured to send data to the DCIC by alternating between (i) first time periods during which the DPIC sends over the bus both produced data and dummy data that together have the fixed data rate of the bus, and (ii) second time periods during which the DPIC sends over the bus only dummy data at the fixed data rate, wherein a rate of the produced date and durations of the first time periods and the second time periods, are preset.