Abstract: An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.

Abstract: An electronic apparatus and a USB interface switching method. The electronic apparatus includes: a first control component corresponding to a first operating system, a second control component corresponding to a second operating system, a USB interface, and a USB interface switching circuit. The first control component is used to detect the data transmission state between the USB interface and the first control component. The second control component is used to detect the data transmission state between the USB interface and the second control component.

Abstract: Disclosed are various examples of providing AI accelerator access as a service at the edge. In some embodiments an artificial intelligence (AI) accelerator device identifier is transmitted to register an AI accelerator with the AI broker service. An AI processing request for the AI accelerator is received from a networked computing device. A bus redirect of the AI accelerator to the networked device is enabled. An AI workload is performed controlled by the networked device through the bus redirect.

Abstract: A semiconductor apparatus that selects a first packet from a plurality of packets stored in a buffer and transfers the first packet. The semiconductor apparatus switches a plurality of different conditions for grouping the plurality of packets according to a priority order of the plurality of conditions; and selects the first packet from a plurality of packets pertaining to a group extracted on a condition selected by the switching according to a given selecting scheme, and transfers the first packet from the buffer.

Abstract: A transmitter device includes a configurable timer circuit that adjusts timing of input data for serial transmission of the input data. The configurable timer circuit may be configured depending on the configured data rate of the transmitter device. In one embodiment, the configurable timer circuit includes a plurality of configurable retimers that retime the input data where at least a portion of one of the plurality of configurable retimers is enabled based on the configured data rate.

Abstract: Techniques comprise receiving results from one or more configuration checks performed on one or more elements of an information processing system, wherein the results are received from a set of one or more interfaces of the information processing system and comprise an indication of detection of a configuration issue with at least a portion of the one or more elements of the information processing system. The method generates one or more remediation actions based on at least a portion of the received results, and then causes initiation of the one or more remediation actions within the information processing system at least in part through the set of one or more interfaces of the information processing system from which the results are received to effectuate remediation of the configuration issue with the portion of the one or more elements of the information processing system.

Abstract: An information handling system may include a host system, a management controller configured to provide out-of-band management of the information handling system, and a network interface controller including a network interface controller storage resource. The management controller may be configured to: receive, from the host system, a first identifier that is specific to an operating system (OS) of the host system; compare the first identifier to a second identifier provided by the network interface controller, wherein the second identifier is specific to an OS of the network interface controller that is stored on the network interface controller storage resource; and in response to a mismatch between the first identifier and the second identifier, prevent the network interface controller from operating.

Abstract: A signal re-driving device, a data storage system and a mode control method are provided. The method includes the following steps. A first signal is received via a receiving circuit of the signal re-driving device. An analog signal feature is detected the receiving circuit. A first mode is entered according to the analog signal feature. The first signal is modulated and a second signal is outputted in the first mode. The second signal is sent via a sending circuit of the signal re-driving device. A digital signal feature is detected via the receiving circuit. And, the first mode is switched to a second mode according to the digital signal feature.

Abstract: A semiconductor device includes an oscillator configured to generate a first clock signal, a first terminal via which an input clock signal is fed in from the outside, a first counter configured to count a clock signal based on the first clock signal between edges in the input clock signal, and a controller configured to send to the oscillator an instruction to adjust the frequency of the first clock signal based on the result of comparison of the count value by the first counter with an expected value.

Abstract: A transceiver device for a user station of a serial bus system, a communication control device, and a method. The transceiver device includes a first terminal for receiving a transmission signal from a communication control device, a transmission module for transmitting the transmission signal onto a bus of the bus system, a reception module for receiving the signal from the bus, the reception module being designed to generate a digital reception signal from the signal received from the bus, a second terminal for sending the digital reception signal to the communication control device and for receiving an operating mode changeover signal from the communication control device, and a changeover feedback block for outputting feedback regarding a changeover of the operating mode that has taken place as a result of the operating mode changeover signal.

Abstract: A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.

Abstract: An interface switching apparatus, communication equipment, and an interface switching method. The first end of the interface converting assembly is connected to a common interface, the second end of the interface converting assembly is connected to the controller, and the interface converting assembly is configured to control the common interface to connect to a target interface of at least two peripheral interfaces according to a control signal sent by the controller; the detection assembly is connected to the controller and the at least two peripheral interfaces, respectively, the detection assembly is configured to detect voltage signals at the at least two peripheral interfaces; the controller is configured to determine, according to the voltage signal, a target interface to which an external device is connected of the at least two peripheral interfaces, generate the control signal, and send the control signal to the interface converting assembly.

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

Abstract: In embodiments, an apparatus for serial communication includes a transceiver, to receive a precoding request from a downlink receiver across a serial communication link, and to transmit data bits to the downlink receiver over the serial communication link. In embodiments, the apparatus further includes a precoder, coupled to the transceiver, to: receive scrambled data bits of a subset of the data bits to be transmitted, from a coupled scrambler, and, in response to the request from the downlink receiver, precode the scrambled data bits, and output the precoded scrambled data bits to the transceiver, for transmission to the downlink receiver across the serial communication link together with other unscrambled data bits.

Abstract: A system and method for efficient communication bus arbitration in a communication protocol are provided. The system and method for efficient communication bus arbitration are a system and method for slave communication bus arbitration in multi-drop communication, and provide efficient and fast communication speed by improving the packet structure in a manner in which a slave controller sequentially responds to a query of a master controller.

Abstract: The present invention provides a DP-out adapter including a decoder, a clock signal generating circuit, a DP signal generating circuit and a symbol counter value comparator. The decoder is configured to decode a USB signal to generate a plurality of packets. The clock signal generating circuit is configured to generate a clock signal. The DP signal generating circuit is configured to generate a DP signal according to the packets, and output the DP signal according to the clock signal. The symbol counter value comparator is configured to generate a first counter value according to a number of symbols corresponding to the plurality of packets, and use the clock signal to count to obtain a second counter value, and compare the first counter value and the second counter value to generate a control signal to the clock signal generating circuit to adjust a frequency of the clock signal.

Abstract: Techniques for data manipulation using processor graph execution using interrupt conservation are disclosed. Processing elements are configured to implement a data flow graph. The processing elements comprise a multilayer graph execution engine. A data engine is loaded with computational parameters for the multilayer graph execution engine. The data engine is coupled to the multilayer graph execution engine, and the computational parameters supply layer-by-layer execution data to the multilayer graph execution engine for data flow graph execution. A first command FIFO is used for loading the data engine with computational parameters, and a second command FIFO is used for loading the multilayer graph execution engine with layer definition data. An input image is provided for a first layer of the multilayer graph execution engine. The data flow graph is executed using the input image and the computational parameters.

Abstract: According to one embodiment, an Information Handling System (IHS) includes at least one storage unit that conforms to an NVMe specification and first and second BMCs. The BMCs are in communication with the storage unit and each configured with computer-executable instructions to negotiate with the second BMC, whether first or second BMC is to be an active BMC such that the other of the first or second BMCs becomes a passive BMC. When the first BMC is the active BMC, allow shared commands to be issued to a storage unit conforming to a Non-Volatile Memory Express (NVMe) specification; otherwise, inhibit the shared commands from being issued to the storage unit.

Abstract: A system includes an interface circuit configured to provide an interface with a link, and a controller. The controller is configured to receive one or more bandwidth requests from one or more clients, and determine at least one of a link speed and a link width for the link based on the one or more bandwidth requests.

Abstract: An electronic device with a connector supporting multiple connection standards includes the connector, a first multiplexer circuit, a processor and a controller. The connector includes a detection pin and at least one signal pin. The first multiplexer circuit is coupled to the at least one signal pin. The processor is coupled to the first multiplexer circuit. The controller monitors the detection pin. The first multiplexer circuit electrically connects the at least one signal pin to the controller. Upon detecting a hot-plug signal occurring at the detection pin, the controller issues a confirmation command via the first multiplexer circuit and the at least one signal pin to request a reply of a device signal. Upon receiving the device signal, the controller controls the first multiplexer circuit according to the device signal to electrically connect the at least one signal pin to the processor or the controller.