Abstract: A transceiver device for a user station of a serial bus system, a communication control device, and a method. The transceiver device includes a first terminal for receiving a transmission signal from a communication control device, a transmission module for transmitting the transmission signal onto a bus of the bus system, a reception module for receiving the signal from the bus, the reception module being designed to generate a digital reception signal from the signal received from the bus, a second terminal for sending the digital reception signal to the communication control device and for receiving an operating mode changeover signal from the communication control device, and a changeover feedback block for outputting feedback regarding a changeover of the operating mode that has taken place as a result of the operating mode changeover signal.

Abstract: A semiconductor device includes an oscillator configured to generate a first clock signal, a first terminal via which an input clock signal is fed in from the outside, a first counter configured to count a clock signal based on the first clock signal between edges in the input clock signal, and a controller configured to send to the oscillator an instruction to adjust the frequency of the first clock signal based on the result of comparison of the count value by the first counter with an expected value.

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

Abstract: An interface switching apparatus, communication equipment, and an interface switching method. The first end of the interface converting assembly is connected to a common interface, the second end of the interface converting assembly is connected to the controller, and the interface converting assembly is configured to control the common interface to connect to a target interface of at least two peripheral interfaces according to a control signal sent by the controller; the detection assembly is connected to the controller and the at least two peripheral interfaces, respectively, the detection assembly is configured to detect voltage signals at the at least two peripheral interfaces; the controller is configured to determine, according to the voltage signal, a target interface to which an external device is connected of the at least two peripheral interfaces, generate the control signal, and send the control signal to the interface converting assembly.

Abstract: The present invention provides a DP-out adapter including a decoder, a clock signal generating circuit, a DP signal generating circuit and a symbol counter value comparator. The decoder is configured to decode a USB signal to generate a plurality of packets. The clock signal generating circuit is configured to generate a clock signal. The DP signal generating circuit is configured to generate a DP signal according to the packets, and output the DP signal according to the clock signal. The symbol counter value comparator is configured to generate a first counter value according to a number of symbols corresponding to the plurality of packets, and use the clock signal to count to obtain a second counter value, and compare the first counter value and the second counter value to generate a control signal to the clock signal generating circuit to adjust a frequency of the clock signal.

Abstract: A system and method for efficient communication bus arbitration in a communication protocol are provided. The system and method for efficient communication bus arbitration are a system and method for slave communication bus arbitration in multi-drop communication, and provide efficient and fast communication speed by improving the packet structure in a manner in which a slave controller sequentially responds to a query of a master controller.

Abstract: In embodiments, an apparatus for serial communication includes a transceiver, to receive a precoding request from a downlink receiver across a serial communication link, and to transmit data bits to the downlink receiver over the serial communication link. In embodiments, the apparatus further includes a precoder, coupled to the transceiver, to: receive scrambled data bits of a subset of the data bits to be transmitted, from a coupled scrambler, and, in response to the request from the downlink receiver, precode the scrambled data bits, and output the precoded scrambled data bits to the transceiver, for transmission to the downlink receiver across the serial communication link together with other unscrambled data bits.

Abstract: According to one embodiment, an Information Handling System (IHS) includes at least one storage unit that conforms to an NVMe specification and first and second BMCs. The BMCs are in communication with the storage unit and each configured with computer-executable instructions to negotiate with the second BMC, whether first or second BMC is to be an active BMC such that the other of the first or second BMCs becomes a passive BMC. When the first BMC is the active BMC, allow shared commands to be issued to a storage unit conforming to a Non-Volatile Memory Express (NVMe) specification; otherwise, inhibit the shared commands from being issued to the storage unit.

Abstract: Techniques for data manipulation using processor graph execution using interrupt conservation are disclosed. Processing elements are configured to implement a data flow graph. The processing elements comprise a multilayer graph execution engine. A data engine is loaded with computational parameters for the multilayer graph execution engine. The data engine is coupled to the multilayer graph execution engine, and the computational parameters supply layer-by-layer execution data to the multilayer graph execution engine for data flow graph execution. A first command FIFO is used for loading the data engine with computational parameters, and a second command FIFO is used for loading the multilayer graph execution engine with layer definition data. An input image is provided for a first layer of the multilayer graph execution engine. The data flow graph is executed using the input image and the computational parameters.

Abstract: A system includes an interface circuit configured to provide an interface with a link, and a controller. The controller is configured to receive one or more bandwidth requests from one or more clients, and determine at least one of a link speed and a link width for the link based on the one or more bandwidth requests.

Abstract: A computing device's performance can be dynamically tuned for a containerized application. A dynamic tuning solution can be configured to identify target applications that are running in workspaces implemented using containers, including when a target application is moved between workspaces and when a workspace's context is changed. The dynamic tuning solution can create mappings between identifiers of the container and a performance level associated with the target applications. A driver can then use these mappings to ensure that the computing device is dynamically tuned to the performance level associated with the target application when the container hosting the target application is active. The dynamic tuning solution can also reconcile discrepancies between a performance level associated with a target application and a performance level associated with a workspace in which the target application is containerized.

Abstract: An electronic device with a connector supporting multiple connection standards includes the connector, a first multiplexer circuit, a processor and a controller. The connector includes a detection pin and at least one signal pin. The first multiplexer circuit is coupled to the at least one signal pin. The processor is coupled to the first multiplexer circuit. The controller monitors the detection pin. The first multiplexer circuit electrically connects the at least one signal pin to the controller. Upon detecting a hot-plug signal occurring at the detection pin, the controller issues a confirmation command via the first multiplexer circuit and the at least one signal pin to request a reply of a device signal. Upon receiving the device signal, the controller controls the first multiplexer circuit according to the device signal to electrically connect the at least one signal pin to the processor or the controller.

Abstract: A flexible processor includes (i) numerous configurable processors interconnected by modular interconnection fabric circuits that are configurable to partition the configurable processors into one or more groups, for parallel execution, and to interconnect the configurable processors in any order for pipelined operations, Each configurable processor may include (i) a control circuit; (ii) numerous configurable arithmetic logic circuits; and (iii) configurable interconnection fabric circuits for interconnecting the configurable arithmetic logic circuits.

Abstract: A register bank of a channel of a direct memory access circuit is initialized. Transfer cycles are executed as configured by the register bank, and updates are made to the registers from a memory. At each transfer cycle, an operation is performed in accordance with a first field of the register bank to either: carry on the execution or generate a first signal and suspend the execution. In response to each reception of the first signal by a central processing unit, an operation is performed to either: generate a second signal or modify the content of the register band and/or record into the memory a first item representative of a next update of the register bank. A second signal is then generated.

Abstract: Embodiments of the present disclosure relate to a method, an electronic device, and a computer program product for implementing a blockchain system on a switch. The method includes establishing a first blockchain node and a second blockchain node on the switch, where the first blockchain node includes a first ingress port and a first egress port, and the second blockchain node includes a second ingress port and a second egress port. The method further includes receiving a broadcast or multicast request from a user device through a user port of the switch. The method further includes sending the broadcast or multicast request to the first ingress port of the first blockchain node and the second ingress port of the second blockchain node. Through the embodiments of the present disclosure, a blockchain system can be implemented on a switch, so as to reduce the latency of the blockchain system.

Abstract: In one embodiment, a method for method for managing a virtual service in an information handling system includes: identifying, by a virtual image of a plurality of virtual images of the virtual service, a device setting to be modified, the device setting associated with a device of the information handling system, each of the plurality of virtual images having respective device settings; accessing, by a host service, a protected namespace of a plurality of protected namespaces, the protected namespace associated with the virtual image; identifying, by the host service, a device index stored in the protected namespace, the device index pointing to a device-specific function associated with the device, the device-specific function stored in a translation table; accessing, by the host service, the device-specific function stored in the translation table based on the device index; and causing, by the host service, the device-specific function to modify the device setting.

Abstract: A method of operating an interface device including a first elastic buffer is provided. The method of operating the interface device includes initializing one or more parameters associated with clock signals for a data transmission or reception of the interface device, checking whether the interface device is in a predetermined mode for adjusting the one or more parameters, adjusting, upon determination that the interface device is in the predetermined mode, the one or more parameters associated with the clock signals of the interface device based on how much of the first buffer or the second buffer is filled with data, and performing the data transmission or reception based on the adjusted one or more parameters associated with the clock signals.

Abstract: In described examples, a voltage regulator includes a processor. A register bank is coupled to the processor. A logic block is coupled to the processor and to the register bank. The logic block receives frames. The processor programs the logic block and the register bank based on at least one of the frames.

Abstract: An electronic device includes a connection unit including a first terminal for receiving power from a power supply apparatus and a second terminal for receiving power supply capability of the power supply apparatus, a communication control unit that performs communication with the power supply apparatus via the second terminal, and a power control unit that performs a process for limiting power supplied from the power supply apparatus to a predetermined power or less in a case where the power supply capability is received from the power supply apparatus.

Abstract: Bus enumeration of a switch fabric bus may be performed without assigning bus numbers to unused switch ports and/or corresponding slots to which the unused switch ports are routed. Accordingly, switches coupled to a switch fabric bus in a chassis may link-train with corresponding slots in the chassis in an attempt to establish active connections with devices coupled to the slots. Unused switch fabric bus lanes running from the switches to unused slots may be identified, and the unused switch ports corresponding to the unused switch fabric bus lanes may be disabled. During a subsequent bus enumeration procedure for the switch fabric bus, bus numbers may be allocated to the identified used switch ports (or corresponding used slots) but not to the identified unused switch ports (or corresponding unused slots). The link training, used/unused switch port identification, and bus enumeration may all be performed each time the chassis is reset.