Patents Examined by Faisal M Zaman
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Patent number: 11693800Abstract: Bandwidth consumption for IO paths between a storage system and host may be managed. It may be determined whether there is congestion on a front-end port (FEP) link. For example, the storage system may monitor for a notification from the switch in accordance with a Fibre Channel (FC) protocol. If a notification is received indicating congestion on an FEP link, the bandwidth thresholds (BWTs) for one or more IO paths between the storage system and one or more hosts that include the FEP link may be reduced. The host port BWTs may continue to be reduced until a congestion notification communication has not been received for a predetermined amount of time, in response to which the host port BWTs for one or more host port links on IO paths that include the FEP link may be increased. Similar techniques may be employed for an FEP link determined to be faulty.Type: GrantFiled: July 13, 2020Date of Patent: July 4, 2023Assignee: EMC IP Holding Company LLCInventors: James Davidson, Alan Rajapa, Scott Rowlands, Igor Fradkin, Arieh Don
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Patent number: 11687114Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.Type: GrantFiled: January 8, 2021Date of Patent: June 27, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Junyoung Park, Young-Hoon Son, Hyun-Yoon Cho, Youngdon Choi, Junghwan Choi
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Patent number: 11675722Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.Type: GrantFiled: June 3, 2021Date of Patent: June 13, 2023Assignee: Apple Inc.Inventors: Sergio Kolor, Sergio V. Tota, Tzach Zemer, Sagi Lahav, Jonathan M. Redshaw, Per H. Hammarlund, Eran Tamari, James Vash, Gaurav Garg, Lior Zimet, Harshavardhan Kaushikkar, Steven Fishwick, Steven R. Hutsell, Shawn M. Fukami
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Patent number: 11657017Abstract: The present disclosure relates to a method comprising receiving edges conveyed by a serial bus and separated by multiples of a same duration, determining a measurement value of a ratio between a cycle time of a clock and the duration, and sending bits on the serial bus using the measurement value.Type: GrantFiled: September 2, 2020Date of Patent: May 23, 2023Assignee: STMicroelectronics (Grenoble 2) SASInventor: Arnaud Dehamel
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Patent number: 11656673Abstract: A memory device includes a hardware suspend mechanism configured to place a component of a memory controller into a lower power mode while a memory operation is being completed. A timer is provided to wakeup the CPU out of the lower power mode; and hardware interrupts can be used in determining to either enter or wake from the lower power mode. Memory monitoring circuitry is provided to estimate the duration of memory operations; and timers are provided to wake the component in the absence of hardware interrupts or additional commands.Type: GrantFiled: December 29, 2020Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Qing Liang, Jonathan Scott Parry, David Aaron Palmer, Stephen Hanna
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Patent number: 11630480Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.Type: GrantFiled: March 13, 2018Date of Patent: April 18, 2023Assignee: Intel CorporationInventors: David J. Harriman, Debendra Das Sharma, Daniel S. Froelich, Sean O. Stalley
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Patent number: 11627004Abstract: An apparatus converts incoming Power over Ethernet signals into power and data communications under the USB type C protocol standards for use with USB type C connections. Embodiments include a control circuit with programmed processes that facilitate negotiation when a USB-C device connector is attempting to communicate with for example, an Ethernet power source. The control circuit identifies the power delivery and communication profiles associated with a USB type C connected device and controls the Power over Ethernet source signal for compatibility with the device's charging profile and compliance under different IEEE standards.Type: GrantFiled: July 15, 2020Date of Patent: April 11, 2023Inventors: Tyler Andrews, Jacky Deng
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Patent number: 11609766Abstract: According to one embodiment, a data processing system performs a secure boot using a security module (e.g., a trusted platform module (TPM)) of a host system. The system verifies that an operating system (OS) and one or more drivers including an accelerator driver associated with a data processing (DP) accelerator is provided by a trusted source. The system launches the accelerator driver within the OS. The system generates a trusted execution environment (TEE) associated with one or more processors of the host system. The system launches an application and a runtime library within the TEE, where the application communicates with the DP accelerator via the runtime library and the accelerator driver.Type: GrantFiled: January 4, 2019Date of Patent: March 21, 2023Assignees: BAIDU USA LLC, BAIDU.COM TIMES TECHNOLOGY (BEIJING) CO., LTD., KUNLUNXIN TECHNOLOGY (BEIJING) COMPANY LIMITEDInventors: Yueqiang Cheng, Yong Liu, Tao Wei, Jian Ouyang
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Patent number: 11609622Abstract: A multi-port Universal Serial Bus Type-C (USB-C) controller with ground and supply cable compensation technologies is described. A USB-C controller includes a first power control circuit (PCU) coupled to a system ground terminal and a first ground terminal and a second PCU coupled to the system ground terminal and a second ground terminal. The first PCU receives a first ground signal indicative of a first ground potential at a first USB-C connector and adjusts a first power voltage line (VBUS) signal on the first VBUS terminal based on the first ground signal and the system ground. The second PCU receives a second ground signal indicative of a second ground potential at a second USB-C connector and adjusts a second VBUS signal on the second VBUS terminal based on the second ground signal and the system ground.Type: GrantFiled: May 12, 2021Date of Patent: March 21, 2023Assignee: Cypress Semiconductor CorporationInventors: Pulkit Shah, Hariom Rai
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Patent number: 11604501Abstract: The present disclosure relates to a method and system to facilitate temperature-aware redistribution of power in a power sourcing device comprising plurality of ports. The method can include monitoring, by using one or more sensors coupled to the power sourcing device, a first temperature associated with a first port of the plurality of ports to obtain a first set of signals and executing, at the power sourcing device, based on a second set of signals obtained from the first set of signals, a first set of instructions associated with redistribution of power from the first port to second port of the plurality of ports, wherein the second set of signals can indicate exceeding of the first temperature above the predefined threshold temperature value.Type: GrantFiled: June 3, 2021Date of Patent: March 14, 2023Assignee: Siliconch Systems Pvt LtdInventors: Siva Naga Subrahmanya Saratchandra Bhagavathula, Munnangi Sirisha, Kaustubh Kumar, Rakesh Kumar Polasa
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Patent number: 11604751Abstract: Embodiments herein describe techniques for preventing a stall when transmitting data between a producer and a consumer in the same integrated circuit (IC). A stall can occur when there is a split point and a convergence point between the producer and consumer. To prevent the stall, the embodiments herein adjust the latencies of one of the paths (or both paths) such that a maximum latency of the shorter path is greater than, or equal to, the minimum latency of the longer path. When this condition is met, this means the shortest path has sufficient buffers (e.g., a sufficient number of FIFOs and registers) to queue/store packets along its length so that a packet can travel along the longer path and reach the convergence point before the buffers in the shortest path are completely full (or just become completely full).Type: GrantFiled: May 10, 2021Date of Patent: March 14, 2023Assignee: XILINX, INC.Inventors: Brian Guttag, Nitin Deshmukh, Sreesan Venkatakrishnan, Satish Sivaswamy
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Patent number: 11599497Abstract: A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.Type: GrantFiled: August 31, 2020Date of Patent: March 7, 2023Assignee: Intel CorporationInventors: Zuoguo Wu, Debendra Das Sharma, Mohiuddin M. Mazumder, Jong-Ru Guo, Anupriya Sriramulu, Narasimha Lanka, Timothy Wig, Jeff Morriss
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Patent number: 11599183Abstract: An electronic device includes a connection unit that receive power from a power supply apparatus via a first terminal, a communication control unit that communicates with the power supply apparatus via a second terminal to receive power supply capability information of the power supply apparatus, and a control unit that disables activation of the electronic device before the communication control unit receives a predetermined notification from the power supply apparatus.Type: GrantFiled: July 28, 2020Date of Patent: March 7, 2023Assignee: CANON KABUSHIKI KAISHAInventors: Yuki Tsujimoto, Hiroki Kitanosako, Masashi Yoshida, Kazuya Miyahara
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Patent number: 11592891Abstract: An information handling system includes resistive short detection circuitry that measures a first amount of power provided by a power supply system, and measures a second amount of power drawn by components. The resistive short detection circuitry compares the first amount of power with the second amount of power. In response to first amount of power being greater than the second amount of power, the resistive short detection circuitry determines that a short exists within the information handling system.Type: GrantFiled: October 15, 2019Date of Patent: February 28, 2023Assignee: Dell Products L.P.Inventors: John Erven Jenne, Kyle E. Cross
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Patent number: 11592884Abstract: Apparatus and methods for managing power consumption of a data-path in a computer system are provided, the data-path comprising a first port and a second port, the first port comprising a high-speed and the second port comprising a low-speed port. The disclosed method including connecting a device to the data-path, determining that the connected device is to communicate using the second port and turning off an active circuit associated with the first port of the data-path.Type: GrantFiled: January 25, 2018Date of Patent: February 28, 2023Assignee: Intel CorporationInventors: Chee Lim Nge, Chia-Hung Kuo, Nivedita Aggarwal, Venkataramani Gopalakrishnan, Robert Gough, Basavaraj Astekar, Vijaykumar Kadgi
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Patent number: 11561919Abstract: Example memory controllers are disclosed. An example memory controller may include a PHY module including a first PHY terminal connected to a plurality of pins of a device connector, a MAC module including a first MAC terminal that is enabled to form a first lane with the first PHY terminal, and a second MAC terminal that is disabled without being connected to the first PHY terminal, a switch controller configured to receive a signal of a host connector connected to the device connector from at least one of the plurality of pins and output a switch signal in response to the signal of the host connector, and a switch configured to disable the second MAC terminal and form the first lane by connecting the first PHY terminal to the first MAC terminal in response to the switch signal.Type: GrantFiled: April 2, 2021Date of Patent: January 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Jong Hoon Kim
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Patent number: 11561601Abstract: A system and method for efficiently transferring data between devices. In various embodiments, a host computing device receives parallel data, encodes the parallel data as a count of pulses as serial data, and conveys the serial data to a peripheral device. The peripheral device decodes the received serial data to determine the parallel data, which is sent to processing logic. The devices send the encoded pluses on a bidirectional line, so the pulses are capable of being sent in both directions. The devices send the encoded pulses on the bidirectional line using a non-zero base voltage level. The devices are capable of using a voltage headroom when conveying encoded pulses between one another. Therefore, a full voltage swing between a ground reference voltage level and a power supply voltage level is not used when conveying the encoded pulses, which reduces power consumption.Type: GrantFiled: June 5, 2020Date of Patent: January 24, 2023Assignee: Apple Inc.Inventor: James M. Hollabaugh
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Patent number: 11556489Abstract: The present application discloses a signal channel switching method, a display terminal and a computer-readable storage medium. The signal channel switching method includes the following operations: establishing a data connection with a first external device connected with a first hot plug pin; obtaining a first voltage detected by a second hot plug pin, and judging whether the first voltage conforms to a preset rule; if the first voltage conforms to the preset rule, obtaining information of a second external device connected with the second hot plug pin; cutting off the data connection with the first external device and establishing a data connection with the second external device according to the information of the second external device.Type: GrantFiled: April 27, 2021Date of Patent: January 17, 2023Assignee: SHENZHEN SKYWORTH-RGB ELECTRONIC CO., LTD.Inventor: Weixiong Pan
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Patent number: 11556493Abstract: A system component having a configurable communication behavior. The system component includes at least one interface for a data bus for the communication with at least one further system component. A defined communications protocol for the transmitting and receiving of data and bus commands is used on the data bus. The communications protocol provides that the at least one further system component queries the communication behavior of the system component via the data bus to adapt its own communication behavior to that of the system component. The system component includes a register for configuration data that define the communication behavior of the system component on the data bus, the register being connected to the data bus so that the configuration data stored in the register are available on the data bus. The function scope of the system component allows for different communication behaviors.Type: GrantFiled: January 9, 2020Date of Patent: January 17, 2023Assignee: Robert Bosch GmbHInventors: Dorde Cvejanovic, Rainer Dorsch
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Patent number: 11531554Abstract: Example implementations relate to performing automated hierarchical configuration tuning for a multi-layer service. According to an example, a service definition and optimization criteria are received for tuning a configuration of a service. The service definition includes information regarding multiple of layers of the service and corresponding configuration groups. An acyclic dependency graph is created including nodes representing each of the of layers and each of the corresponding configuration groups.Type: GrantFiled: December 10, 2019Date of Patent: December 20, 2022Assignee: salesforce.com, inc.Inventors: Ajay Krishna Borra, Himanshu Mittal, Metarya Ruparel, Ravi Teja Pothana, Manpreet Singh