Abstract: A method and apparatus are provided for assigning transport priorities to messages in a data processing system. An incoming message at an input/output (I/O) interface of the data processing system includes a message identifier and payload data. Match information, including an indicator or whether the message identifier of the incoming message matches an identifier of a request in a receive queue (RQ), is used to assign a transport priority value to the incoming message. The incoming message is transported to the destination node through an interconnect structure dependent upon the assigned transport priority value.

Abstract: In one or more embodiments, one or more systems, processes, and/or methods may determine first power supply units associated with a first power supply grid of power supply grids that are configured to provide power to information handling systems (IHSs) and second power supply units associated with a second power supply grid of the power supply grids; may determine that the power supply grids are configured for grid redundancy; may determine that a number of operational power supply units of the first power supply units meets a minimum number of operational power supply units to provide power to the IHSs; may determine that a number of operational power supply units of the second power supply units not the minimum number of operational power supply units; and may suppress an alert of at least one of the second power supply units that is not operational to provide power to the IHSs.

Abstract: Techniques for processing I/O operations may include: receiving an I/O having an associated expected execution time (EET) and I/O service level; selecting, in accordance with the EET and service level of the I/O, a first I/O queue from multiple pending I/O queues; inserting the I/O into the first I/O queue; and performing I/O shifting. I/O shifting may include shifting I/Os from one pending I/O queue to another that is ranked immediately higher than the one pending I/O queue. The multiple I/O queues may be ranked from a highest priority queue to a lowest priority queue. I/O shifting may shift I/Os from the highest priority queue to execution and shifting I/Os from another queue into the highest priority queue. I/O shifting is subject to remaining credits available of the multiple I/O queues and time distance between source and target queues.

Abstract: In embodiments, an apparatus for serial communication includes a transceiver, to receive a precoding request from a downlink receiver across a serial communication link, and to transmit data bits to the downlink receiver over the serial communication link. In embodiments, the apparatus further includes a precoder, coupled to the transceiver, to: receive scrambled data bits of a subset of the data bits to be transmitted, from a coupled scrambler, and, in response to the request from the downlink receiver, precode the scrambled data bits, and output the precoded scrambled data bits to the transceiver, for transmission to the downlink receiver across the serial communication link together with other unscrambled data bits.

Abstract: Provided are a method and apparatus for controlling a hot plug operation of a CPU in a mobile terminal. The method includes: adjusting (101) at least one temperature threshold of the CPU when detecting that a number of hot plug operations of the CPU within a preset period is greater than a preset threshold, where the temperature threshold is used for controlling the hot plug operations of the CPU; and controlling (102) the hot plug operation of the CPU by use of the adjusted temperature threshold.

Abstract: Provided are a system and related devices whereby it is easy to achieve I/O virtualization. A HUB device according to the present invention is provided with a switch for internal slots in a PC (for example, internal PCI-Express slots) and is configured to be able to interconnect internal slots in other PCs. In a computer system in which one or more PCs are interconnected by this HUB device, which serves as the central point of connection, each PC can “see” I/O devices of other PCs through the switch for the internal slots. Therefore, each PC creates a device list including I/O devices of the PC and I/O devices of other PCs, and the OS of the PC uses the device list. As a result, it is possible to easily achieve I/O virtualization.

Abstract: An interface assembly of a host system that connects a peripheral device to a USB Type-C interface has at least one supply line and at least one signaling line, wherein one from among a plurality of different power profiles can be selected by the peripheral device by applying different analog control signals to the signaling line, a signaling circuit connects to the signaling line on a side of the host system, the signaling circuit, on the basis of at least one digital control signal, produces a predetermined analog control signal assigned to the at least one digital control signal and outputs it to the peripheral device via the signaling line and the at least one digital control signal is provided via a GPIO port of a control module of a system component of the host system, and the GPIO port is controlled by a BIOS.

Abstract: Systems, methods, and apparatuses relating to multicast in a configurable spatial accelerator are described. In one embodiment, an accelerator includes a first output buffer of a first processing element coupled to a first input buffer of a second processing element and a second input buffer of a third processing element; and the first processing element determines that it was able to complete a transmission in a previous cycle when the first processing element observed for both the second processing element and the third processing element that either a speculation value was set to a value to indicate a dataflow token was stored in its input buffer (e.g., as indicated by a reception value (e.g., bit)) or a backpressure value was set to a value to indicate that storage is to be available in its input buffer before dequeuing the dataflow token from the first output buffer.

Abstract: A direct memory access (DMA) engine may be responsible to enable and control DMA data flow within a computing system. The DMA engine moves blocks of data, associated with descriptors in a plurality of queues, from a source to a destination memory location or address, autonomously from control by a computer system's processor. Based on analysis of the data blocks linked to the descriptors in the queues, the DMA engine and its associated DMA fragmenter ensure that data blocks stored linked to descriptors in the queues do not remain idle for an exorbitant period of time. The DMA fragmenter may divide large data blocks into smaller data blocks to ensure that the processing of large data blocks does not preclude the timely processing of smaller data blocks associated with one or more descriptors in the queues. The data blocks stored may be two-dimensional data blocks.

Abstract: Embodiments for managing High-Definition Multimedia Interface (HDMI) data are provided. HDMI data is received at an HDMI connector of an HDMI device. The HDMI data received at the HDMI connector is transmitted to another HDMI connector of the HDMI device. The transmission of the HDMI data received at the HDMI connector to the other HDMI connector of the HDMI device is ceased during the receiving of the HDMI data at the HDMI connector of the HDMI device.

Abstract: According to examples, an apparatus may include a memory to which a first queue and a second queue are assigned, in which a storage device is to access data task requests stored in the first queue and the second queue, in which the apparatus is to transfer the first queue to a second apparatus. The apparatus may also include a central processing unit (CPU), the CPU to input data task requests for the storage device into the second queue, in which the second apparatus is to store the first queue in a second memory of the second apparatus, and the storage device is to access data task requests from the first queue stored in the second memory of the second apparatus and data task requests from the second queue stored in the memory to cause the apparatus and the second apparatus to share access to the storage device.

Abstract: In accordance with embodiments of the present disclosure, an adapter for different types of devices that are defined by a full set of capabilities for a communication protocol may include one or more ports, wherein each of the one or more ports is configured to receive one of the different types of devices, and a device controller communicatively coupled to the one or more ports. The device controller may be configured to, when one of the different types of devices is received by the one or more ports obtain information related to a detection of the one of the different types of devices and, based on the information related to the detection, expose a subset of capabilities from the full set of capabilities to a bus of the communication protocol, wherein the subset of capabilities is defined by the one of the different types of devices for the communication protocol.

Abstract: In conventional systems with a plurality of UFS devices daisy-chained to a UFS host, a UFS device driver must be able to differentiate among the links, and send either link control messages or data/management (D/M) messages to a UFS host controller. This can make force the UFS device driver to be complicated and error prone. To address this issue, a host controller can provide a uniform view of a plurality of daisy-chained devices to a device driver of a host. For example, the host controller can be such that from the perspective of the device driver, each device can appear to be a point-to-point connected device. This can allow the device driver to use a same set of link control messages to control the links. In this way, the device driver can be simplified and thus less error prone.

Abstract: A first I/O controller of a storage server sends a first command to a first solid state drive (SSD) of the storage server via a first submission queue of the first SSD, wherein the first command is a first read command or a first write command. The first I/O controller receives a first acknowledgement from the first SSD that the first command has been completed via a first completion queue of the first SSD. A second I/O controller of the storage server sends a second command to the first SSD of the storage server via a second submission queue of the first SSD, wherein the second command is a second read command or a second write command. The second I/O controller receives a second acknowledgement from the first SSD that the second command has been completed via a second completion queue of the first SSD.

Abstract: A bus control circuit includes: a plurality of queues that each include a plurality of entries for storing data, a first read pointer, and a check pointer set to indicate a same entry as an entry indicated by the first read pointer, and each store data on a First in, First out basis; a plurality of first arbitration circuits that receive, in a divided manner, arbitration participation signals from the plurality of queues, each arbitrate the received plurality of arbitration participation signals, and each output one of the plurality of arbitration participation signals; a plurality of buffers that each store, on the First in, First out basis, the arbitration participation signals output from the respective first arbitration circuits; and a second arbitration circuit that arbitrates the arbitration participation signals output from the plurality of buffers and outputs an arbitration result signal corresponding to one of the plurality of queues.

Abstract: Various embodiments are disclosed for automatic transmission of dummy bits in a serial bus master. The disclosed embodiments allow a single DMA descriptor to be fetched from memory for the reception of a specified amount of data. Dummy bits can be located or generated in the serial bus master either as a user configurable value or a default value. Logic in the serial bus master initiates a data transfer by writing a count value representing an amount of data to be received to a count register in the serial bus master. The single DMA descriptor is then configured to handle the internal transfer of bits received by the serial bus master from a serial bus slave and the DMA controller is enabled. When data transfer is initiated, the serial bus master starts sending dummy bits to the serial bus slave and receiving data bits from the serial bus slave.

Abstract: The present disclosure relates to a distributed console server system. The system may have a server and a software module loaded onto the server for communications with a plurality of remote devices within a data center. A remote serial port unit may be included which is in communication with the server and which is controlled in part by the server and the software module. The remote serial port unit may be in communication with the plurality of remote devices. The remote serial port unit may include at least one of a first module including a plurality of RJ45 ports, or a second module including a plurality of USB ports.

Abstract: An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.

Abstract: Embodiments of a peripheral component are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors in one peripheral component can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

Abstract: A unified communication platform for computer peripherals enables one peripheral device of a plurality of devices to communicate and control one or more of the other peripheral devices of the plurality of devices, wherein the plurality of devices are associated with a host device, according to certain embodiments.